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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : jhr 1117 (* x86.sml
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 : leunga 797 structure MLTreeUtils : MLTREE_UTILS
43 : george 933 where T = X86Instr.T
44 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
45 : george 933 where I = X86Instr and T = X86Instr.T
46 : george 984 structure MLTreeStream : MLTREE_STREAM
47 :     where T = ExtensionComp.T
48 : george 545 datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
49 :     val arch : arch ref
50 : leunga 593 val cvti2f :
51 : leunga 815 {ty: X86Instr.T.ty,
52 :     src: X86Instr.operand,
53 :     (* source operand, guaranteed to be non-memory! *)
54 :     an: Annotations.annotations ref (* cluster annotations *)
55 :     } ->
56 : leunga 593 {instrs : X86Instr.instruction list,(* the instructions *)
57 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
58 :     cleanup: X86Instr.instruction list (* cleanup code *)
59 :     }
60 : leunga 731 (* When the following flag is set, we allocate floating point registers
61 :     * directly on the floating point stack
62 :     *)
63 :     val fast_floating_point : bool ref
64 : george 545 ) : sig include MLTREECOMP
65 :     val rewriteMemReg : bool
66 :     end =
67 : monnier 247 struct
68 : leunga 775 structure I = X86Instr
69 :     structure T = I.T
70 : george 984 structure TS = ExtensionComp.TS
71 : george 545 structure C = I.C
72 :     structure Shuffle = Shuffle(I)
73 : monnier 247 structure W32 = Word32
74 : george 545 structure A = MLRiscAnnotations
75 : george 909 structure CFG = ExtensionComp.CFG
76 : george 889 structure CB = CellsBasis
77 : monnier 247
78 : george 984 type instrStream = (I.instruction,C.cellset,CFG.cfg) TS.stream
79 :     type mltreeStream = (T.stm,T.mlrisc list,CFG.cfg) TS.stream
80 : leunga 565
81 :     datatype kind = REAL | INTEGER
82 : george 545
83 :     structure Gen = MLTreeGen
84 :     (structure T = T
85 : jhr 1117 structure Cells = C
86 : george 545 val intTy = 32
87 :     val naturalWidths = [32]
88 :     datatype rep = SE | ZE | NEITHER
89 :     val rep = NEITHER
90 :     )
91 :    
92 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
93 : monnier 247
94 : george 545 (* Should we perform automatic MemReg translation?
95 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
96 :     *)
97 :     val rewriteMemReg = rewriteMemReg
98 : leunga 731
99 :     (* The following hardcoded *)
100 : leunga 744 fun isMemReg r = rewriteMemReg andalso
101 : george 889 let val r = CB.registerNum r
102 : leunga 744 in r >= 8 andalso r < 32
103 :     end
104 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
105 : george 889 then let val r = CB.registerNum r
106 : leunga 744 in r >= 8 andalso r < 32 end
107 : leunga 731 else true
108 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
109 : george 889 let val r = CB.registerNum r
110 : leunga 744 in r >= 8 andalso r < 32 end
111 :     )
112 : monnier 247
113 : george 555 val ST0 = C.ST 0
114 :     val ST7 = C.ST 7
115 : leunga 797 val one = T.I.int_1
116 : george 555
117 : leunga 797 val opcodes8 = {INC=I.INCB,DEC=I.DECB,ADD=I.ADDB,SUB=I.SUBB,
118 :     NOT=I.NOTB,NEG=I.NEGB,
119 :     SHL=I.SHLB,SHR=I.SHRB,SAR=I.SARB,
120 :     OR=I.ORB,AND=I.ANDB,XOR=I.XORB}
121 :     val opcodes16 = {INC=I.INCW,DEC=I.DECW,ADD=I.ADDW,SUB=I.SUBW,
122 :     NOT=I.NOTW,NEG=I.NEGW,
123 :     SHL=I.SHLW,SHR=I.SHRW,SAR=I.SARW,
124 :     OR=I.ORW,AND=I.ANDW,XOR=I.XORW}
125 :     val opcodes32 = {INC=I.INCL,DEC=I.DECL,ADD=I.ADDL,SUB=I.SUBL,
126 :     NOT=I.NOTL,NEG=I.NEGL,
127 :     SHL=I.SHLL,SHR=I.SHRL,SAR=I.SARL,
128 :     OR=I.ORL,AND=I.ANDL,XOR=I.XORL}
129 :    
130 : george 545 (*
131 :     * The code generator
132 :     *)
133 : monnier 411 fun selectInstructions
134 : george 545 (instrStream as
135 : george 1003 TS.S.STREAM{emit=emitInstruction,defineLabel,entryLabel,pseudoOp,
136 :     annotation,getAnnotations,beginCluster,endCluster,exitBlock,comment,...}) =
137 :     let
138 :     val emit = emitInstruction o I.INSTR
139 :     exception EA
140 : monnier 411
141 : george 545 (* label where a trap is generated -- one per cluster *)
142 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
143 : monnier 247
144 : leunga 731 (* flag floating point generation *)
145 :     val floatingPointUsed = ref false
146 :    
147 : george 545 (* effective address of an integer register *)
148 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
149 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
150 : monnier 411
151 : george 545 (* Add an overflow trap *)
152 :     fun trap() =
153 :     let val jmp =
154 :     case !trapLabel of
155 : george 909 NONE => let val label = Label.label "trap" ()
156 : george 1003 val jmp = I.jcc{cond=I.O,
157 : leunga 775 opnd=I.ImmedLabel(T.LABEL label)}
158 : george 545 in trapLabel := SOME(jmp, label); jmp end
159 :     | SOME(jmp, _) => jmp
160 : george 1003 in emitInstruction jmp end
161 : monnier 411
162 : george 545 val newReg = C.newReg
163 :     val newFreg = C.newFreg
164 : monnier 247
165 : leunga 731 fun fsize 32 = I.FP32
166 :     | fsize 64 = I.FP64
167 :     | fsize 80 = I.FP80
168 :     | fsize _ = error "fsize"
169 :    
170 : george 545 (* mark an expression with a list of annotations *)
171 : george 1009 fun mark'(i,[]) = emitInstruction(i)
172 : george 545 | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
173 : monnier 247
174 : george 545 (* annotate an expression and emit it *)
175 : george 1009 fun mark(i,an) = mark'(I.INSTR i,an)
176 : monnier 247
177 : george 1003 val emits = app emitInstruction
178 : leunga 731
179 : george 545 (* emit parallel copies for integers
180 :     * Translates parallel copies that involve memregs into
181 :     * individual copies.
182 :     *)
183 :     fun copy([], [], an) = ()
184 :     | copy(dst, src, an) =
185 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
186 : george 889 if CB.sameColor(rd,rs) then [] else
187 : george 545 let val tmpR = I.Direct(newReg())
188 : george 1003 in [I.move{mvOp=I.MOVL, src=src, dst=tmpR},
189 :     I.move{mvOp=I.MOVL, src=tmpR, dst=dst}]
190 : george 545 end
191 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
192 : george 889 if CB.sameColor(rd,rs) then []
193 : george 1009 else [I.COPY{k=CB.GP, sz=32, dst=[rd], src=[rs], tmp=NONE}]
194 : george 1003 | mvInstr{dst, src} = [I.move{mvOp=I.MOVL, src=src, dst=dst}]
195 : george 545 in
196 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
197 : leunga 744 {tmp=SOME(I.Direct(newReg())),
198 : george 545 dst=dst, src=src})
199 :     end
200 :    
201 :     (* conversions *)
202 :     val itow = Word.fromInt
203 :     val wtoi = Word.toInt
204 : george 761 fun toInt32 i = T.I.toInt32(32, i)
205 : george 545 val w32toi32 = Word32.toLargeIntX
206 :     val i32tow32 = Word32.fromLargeInt
207 : monnier 247
208 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
209 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
210 : monnier 247
211 : george 545 (* some useful registers *)
212 :     val eax = I.Direct(C.eax)
213 :     val ecx = I.Direct(C.ecx)
214 :     val edx = I.Direct(C.edx)
215 : monnier 247
216 : leunga 775 fun immedLabel lab = I.ImmedLabel(T.LABEL lab)
217 : george 545
218 :     (* Is the expression zero? *)
219 : george 761 fun isZero(T.LI z) = T.I.isZero z
220 : george 545 | isZero(T.MARK(e,a)) = isZero e
221 :     | isZero _ = false
222 :     (* Does the expression set the zero bit?
223 :     * WARNING: we assume these things are not optimized out!
224 :     *)
225 :     fun setZeroBit(T.ANDB _) = true
226 :     | setZeroBit(T.ORB _) = true
227 :     | setZeroBit(T.XORB _) = true
228 :     | setZeroBit(T.SRA _) = true
229 :     | setZeroBit(T.SRL _) = true
230 :     | setZeroBit(T.SLL _) = true
231 : leunga 695 | setZeroBit(T.SUB _) = true
232 :     | setZeroBit(T.ADDT _) = true
233 :     | setZeroBit(T.SUBT _) = true
234 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
235 :     | setZeroBit _ = false
236 : monnier 247
237 : leunga 695 fun setZeroBit2(T.ANDB _) = true
238 :     | setZeroBit2(T.ORB _) = true
239 :     | setZeroBit2(T.XORB _) = true
240 :     | setZeroBit2(T.SRA _) = true
241 :     | setZeroBit2(T.SRL _) = true
242 :     | setZeroBit2(T.SLL _) = true
243 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
244 :     | setZeroBit2(T.SUB _) = true
245 :     | setZeroBit2(T.ADDT _) = true
246 :     | setZeroBit2(T.SUBT _) = true
247 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
248 :     | setZeroBit2 _ = false
249 :    
250 : leunga 731 (* emit parallel copies for floating point
251 :     * Normal version.
252 :     *)
253 :     fun fcopy'(fty, [], [], _) = ()
254 :     | fcopy'(fty, dst as [_], src as [_], an) =
255 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,src=src,tmp=NONE}, an)
256 : leunga 731 | fcopy'(fty, dst, src, an) =
257 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
258 : monnier 247
259 : leunga 731 (* emit parallel copies for floating point.
260 :     * Fast version.
261 :     * Translates parallel copies that involve memregs into
262 :     * individual copies.
263 :     *)
264 :    
265 :     fun fcopy''(fty, [], [], _) = ()
266 :     | fcopy''(fty, dst, src, an) =
267 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
268 :     let val fsize = fsize fty
269 : george 1003 fun mvInstr{dst, src} = [I.fmove{fsize=fsize, src=src, dst=dst}]
270 : leunga 731 in
271 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
272 : leunga 744 {tmp=case dst of
273 : leunga 731 [_] => NONE
274 :     | _ => SOME(I.FPR(newReg())),
275 :     dst=dst, src=src})
276 :     end
277 :     else
278 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,
279 :     src=src,tmp=
280 : leunga 731 case dst of
281 :     [_] => NONE
282 :     | _ => SOME(I.FPR(newFreg()))}, an)
283 :    
284 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
285 :     then fcopy'' x else fcopy' x
286 :    
287 : george 545 (* Translates MLTREE condition code to x86 condition code *)
288 :     fun cond T.LT = I.LT | cond T.LTU = I.B
289 :     | cond T.LE = I.LE | cond T.LEU = I.BE
290 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
291 :     | cond T.GE = I.GE | cond T.GEU = I.AE
292 :     | cond T.GT = I.GT | cond T.GTU = I.A
293 : jhr 1119 | cond cc = error(concat["cond(", T.Basis.condToString cc, ")"])
294 : monnier 247
295 : leunga 815 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
296 :    
297 : george 545 (* Move and annotate *)
298 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
299 : george 889 if CB.sameColor(s,d) then ()
300 : george 1009 else mark'(I.COPY{k=CB.GP, sz=32, dst=[d], src=[s], tmp=NONE}, an)
301 : leunga 815 | move'(I.Immed 0, dst as I.Direct d, an) =
302 :     mark(I.BINARY{binOp=I.XORL, src=dst, dst=dst}, an)
303 : george 545 | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
304 : monnier 247
305 : george 545 (* Move only! *)
306 :     fun move(src, dst) = move'(src, dst, [])
307 : monnier 247
308 : george 545 val readonly = I.Region.readonly
309 : monnier 247
310 : george 545 (*
311 : george 761 * Compute an effective address.
312 : george 545 *)
313 : george 761 fun address(ea, mem) = let
314 : george 545 (* Keep building a bigger and bigger effective address expressions
315 :     * The input is a list of trees
316 :     * b -- base
317 :     * i -- index
318 :     * s -- scale
319 :     * d -- immed displacement
320 :     *)
321 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
322 :     | doEA(t::trees, b, i, s, d) =
323 :     (case t of
324 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
325 : leunga 775 | T.CONST _ => doEALabel(trees, t, b, i, s, d)
326 :     | T.LABEL _ => doEALabel(trees, t, b, i, s, d)
327 :     | T.LABEXP le => doEALabel(trees, le, b, i, s, d)
328 : george 545 | T.ADD(32, t1, t2 as T.REG(_,r)) =>
329 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
330 :     else doEA(t1::t2::trees, b, i, s, d)
331 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
332 :     | T.SUB(32, t1, T.LI n) =>
333 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
334 :     | T.SLL(32, t1, T.LI n) => let
335 :     val n = T.I.toInt(32, n)
336 :     in
337 :     case n
338 :     of 0 => displace(trees, t1, b, i, s, d)
339 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
340 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
341 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
342 :     | _ => displace(trees, t, b, i, s, d)
343 :     end
344 : george 545 | t => displace(trees, t, b, i, s, d)
345 :     )
346 : monnier 247
347 : george 545 (* Add an immed constant *)
348 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
349 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
350 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
351 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
352 : leunga 775 doEA(trees, b, i, s,
353 :     I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, n)))))
354 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
355 : monnier 247
356 : george 545 (* Add a label expression *)
357 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
358 :     doEA(trees, b, i, s, I.ImmedLabel le)
359 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
360 :     doEA(trees, b, i, s,
361 : leunga 775 I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, m))))
362 : george 545 handle Overflow => error "doEALabel: constant too large")
363 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
364 : leunga 775 doEA(trees, b, i, s, I.ImmedLabel(T.ADD(32,le,le')))
365 : george 545 | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
366 : monnier 247
367 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
368 :     | makeAddressingMode(SOME base, NONE, _, disp) =
369 :     I.Displace{base=base, disp=disp, mem=mem}
370 :     | makeAddressingMode(base, SOME index, scale, disp) =
371 : george 761 I.Indexed{base=base, index=index, scale=scale,
372 : george 545 disp=disp, mem=mem}
373 : monnier 247
374 : george 545 (* generate code for tree and ensure that it is not in %esp *)
375 :     and exprNotEsp tree =
376 :     let val r = expr tree
377 : george 889 in if CB.sameColor(r, C.esp) then
378 : george 545 let val tmp = newReg()
379 :     in move(I.Direct r, I.Direct tmp); tmp end
380 :     else r
381 :     end
382 : monnier 247
383 : george 545 (* Add a base register *)
384 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
385 :     doEA(trees, SOME(expr t), i, s, d)
386 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
387 :     (* make t the index, but make sure that it is not %esp! *)
388 :     let val i = expr t
389 : george 889 in if CB.sameColor(i, C.esp) then
390 : george 545 (* swap base and index *)
391 : george 889 if CB.sameColor(base, C.esp) then
392 : george 545 doEA(trees, SOME i, b, 0, d)
393 :     else (* base and index = %esp! *)
394 :     let val index = newReg()
395 :     in move(I.Direct i, I.Direct index);
396 :     doEA(trees, b, SOME index, 0, d)
397 :     end
398 :     else
399 :     doEA(trees, b, SOME i, 0, d)
400 :     end
401 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
402 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
403 :     in doEA(trees, SOME b, i, s, d) end
404 : monnier 247
405 : george 545 (* Add an indexed register *)
406 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
407 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
408 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
409 :     doEA(trees, SOME(expr t0), i, s, d)
410 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
411 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
412 :     in doEA(trees, SOME b, i, s, d) end
413 :    
414 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
415 :     I.Immed _ => raise EA
416 :     | I.ImmedLabel le => I.LabelEA le
417 :     | ea => ea
418 :     end (* address *)
419 : monnier 247
420 : george 545 (* reduce an expression into an operand *)
421 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
422 : leunga 775 | operand(x as (T.CONST _ | T.LABEL _)) = I.ImmedLabel x
423 :     | operand(T.LABEXP le) = I.ImmedLabel le
424 : george 545 | operand(T.REG(_,r)) = IntReg r
425 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
426 :     | operand(t) = I.Direct(expr t)
427 : monnier 247
428 : george 545 and moveToReg(opnd) =
429 :     let val dst = I.Direct(newReg())
430 :     in move(opnd, dst); dst
431 :     end
432 : monnier 247
433 : george 545 and reduceOpnd(I.Direct r) = r
434 :     | reduceOpnd opnd =
435 :     let val dst = newReg()
436 :     in move(opnd, I.Direct dst); dst
437 :     end
438 : monnier 247
439 : george 545 (* ensure that the operand is either an immed or register *)
440 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
441 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
442 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
443 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
444 :     | immedOrReg opnd = opnd
445 : monnier 247
446 : george 545 and isImmediate(I.Immed _) = true
447 :     | isImmediate(I.ImmedLabel _) = true
448 :     | isImmediate _ = false
449 : monnier 247
450 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
451 :    
452 :     and isMemOpnd opnd =
453 :     (case opnd of
454 :     I.Displace _ => true
455 :     | I.Indexed _ => true
456 :     | I.MemReg _ => true
457 :     | I.LabelEA _ => true
458 : george 555 | I.FDirect f => true
459 : george 545 | _ => false
460 :     )
461 :    
462 :     (*
463 :     * Compute an integer expression and put the result in
464 :     * the destination register rd.
465 :     *)
466 : george 889 and doExpr(exp, rd : CB.cell, an) =
467 : george 545 let val rdOpnd = IntReg rd
468 : monnier 247
469 : george 889 fun equalRd(I.Direct r) = CB.sameColor(r, rd)
470 :     | equalRd(I.MemReg r) = CB.sameColor(r, rd)
471 : george 545 | equalRd _ = false
472 : monnier 247
473 : george 545 (* Emit a binary operator. If the destination is
474 :     * a memReg, do something smarter.
475 :     *)
476 :     fun genBinary(binOp, opnd1, opnd2) =
477 :     if isMemReg rd andalso
478 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
479 :     equalRd(opnd2)
480 :     then
481 :     let val tmpR = newReg()
482 :     val tmp = I.Direct tmpR
483 :     in move(opnd1, tmp);
484 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
485 :     move(tmp, rdOpnd)
486 :     end
487 :     else
488 :     (move(opnd1, rdOpnd);
489 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
490 :     )
491 : monnier 247
492 : george 545 (* Generate a binary operator; it may commute *)
493 :     fun binaryComm(binOp, e1, e2) =
494 :     let val (opnd1, opnd2) =
495 :     case (operand e1, operand e2) of
496 :     (x as I.Immed _, y) => (y, x)
497 :     | (x as I.ImmedLabel _, y) => (y, x)
498 :     | (x, y as I.Direct _) => (y, x)
499 :     | (x, y) => (x, y)
500 :     in genBinary(binOp, opnd1, opnd2)
501 :     end
502 :    
503 :     (* Generate a binary operator; non-commutative *)
504 :     fun binary(binOp, e1, e2) =
505 :     genBinary(binOp, operand e1, operand e2)
506 :    
507 :     (* Generate a unary operator *)
508 :     fun unary(unOp, e) =
509 :     let val opnd = operand e
510 :     in if isMemReg rd andalso isMemOpnd opnd then
511 :     let val tmp = I.Direct(newReg())
512 :     in move(opnd, tmp); move(tmp, rdOpnd)
513 :     end
514 :     else move(opnd, rdOpnd);
515 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
516 :     end
517 :    
518 :     (* Generate shifts; the shift
519 :     * amount must be a constant or in %ecx *)
520 :     fun shift(opcode, e1, e2) =
521 :     let val (opnd1, opnd2) = (operand e1, operand e2)
522 :     in case opnd2 of
523 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
524 :     | _ =>
525 :     if equalRd(opnd2) then
526 :     let val tmpR = newReg()
527 :     val tmp = I.Direct tmpR
528 :     in move(opnd1, tmp);
529 :     move(opnd2, ecx);
530 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
531 :     move(tmp, rdOpnd)
532 :     end
533 :     else
534 :     (move(opnd1, rdOpnd);
535 :     move(opnd2, ecx);
536 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
537 :     )
538 :     end
539 :    
540 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
541 :     fun divrem(signed, overflow, e1, e2, resultReg) =
542 :     let val (opnd1, opnd2) = (operand e1, operand e2)
543 :     val _ = move(opnd1, eax)
544 : leunga 815 val oper = if signed then (emit(I.CDQ); I.IDIVL1)
545 :     else (zero edx; I.DIVL1)
546 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
547 :     move(resultReg, rdOpnd);
548 :     if overflow then trap() else ()
549 :     end
550 :    
551 :     (* Optimize the special case for division *)
552 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
553 :     val n = toInt32 n'
554 :     val w = T.I.toWord32(32, n')
555 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
556 : george 545 fun log2 n = (* n must be > 0!!! *)
557 :     let fun loop(0w1,pow) = pow
558 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
559 : george 545 in loop(n,0) end
560 :     in if n > 1 andalso isPowerOf2 w then
561 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
562 : george 545 in if signed then
563 :     (* signed; simulate round towards zero *)
564 : george 909 let val label = Label.anon()
565 : george 545 val reg1 = expr e1
566 :     val opnd1 = I.Direct reg1
567 :     in if setZeroBit e1 then ()
568 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
569 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
570 :     emit(if n = 2 then
571 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
572 :     else
573 :     I.BINARY{binOp=I.ADDL,
574 : george 761 src=I.Immed(n - 1),
575 : george 545 dst=opnd1});
576 :     defineLabel label;
577 :     shift(I.SARL, T.REG(32, reg1), pow)
578 :     end
579 :     else (* unsigned *)
580 :     shift(I.SHRL, e1, pow)
581 :     end
582 :     else
583 :     (* note the only way we can overflow is if
584 :     * n = 0 or n = -1
585 :     *)
586 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
587 :     e1, e2, eax)
588 :     end
589 :     | divide(signed, overflow, e1, e2) =
590 :     divrem(signed, overflow, e1, e2, eax)
591 : monnier 247
592 : george 545 fun rem(signed, overflow, e1, e2) =
593 :     divrem(signed, overflow, e1, e2, edx)
594 : leunga 815
595 :     (* Makes sure the destination must be a register *)
596 :     fun dstMustBeReg f =
597 :     if isMemReg rd then
598 :     let val tmpR = newReg()
599 :     val tmp = I.Direct(tmpR)
600 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
601 :     else f(rd, rdOpnd)
602 :    
603 : george 545 (* unsigned integer multiplication *)
604 :     fun uMultiply(e1, e2) =
605 :     (* note e2 can never be (I.Direct edx) *)
606 :     (move(operand e1, eax);
607 : leunga 815 mark(I.MULTDIV{multDivOp=I.MULL1,
608 : george 545 src=regOrMem(operand e2)},an);
609 :     move(eax, rdOpnd)
610 :     )
611 :    
612 :     (* signed integer multiplication:
613 :     * The only forms that are allowed that also sets the
614 :     * OF and CF flags are:
615 :     *
616 : leunga 815 * (dst) (src1) (src2)
617 : george 545 * imul r32, r32/m32, imm8
618 : leunga 815 * (dst) (src)
619 : george 545 * imul r32, imm8
620 :     * imul r32, imm32
621 : leunga 815 * imul r32, r32/m32
622 :     * Note: destination must be a register!
623 : george 545 *)
624 :     fun multiply(e1, e2) =
625 : leunga 815 dstMustBeReg(fn (rd, rdOpnd) =>
626 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _) =
627 :     (move(i1, rdOpnd);
628 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=i2},an))
629 :     | doit(rm, i2 as I.Immed _) = doit(i2, rm)
630 :     | doit(imm as I.Immed(i), rm) =
631 :     mark(I.MUL3{dst=rd, src1=rm, src2=i},an)
632 :     | doit(r1 as I.Direct _, r2 as I.Direct _) =
633 :     (move(r1, rdOpnd);
634 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=r2},an))
635 :     | doit(r1 as I.Direct _, rm) =
636 :     (move(r1, rdOpnd);
637 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm},an))
638 :     | doit(rm, r as I.Direct _) = doit(r, rm)
639 :     | doit(rm1, rm2) =
640 : george 545 if equalRd rm2 then
641 :     let val tmpR = newReg()
642 :     val tmp = I.Direct tmpR
643 :     in move(rm1, tmp);
644 : leunga 815 mark(I.BINARY{binOp=I.IMULL, dst=tmp, src=rm2},an);
645 :     move(tmp, rdOpnd)
646 : george 545 end
647 :     else
648 : leunga 815 (move(rm1, rdOpnd);
649 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm2},an)
650 : george 545 )
651 :     val (opnd1, opnd2) = (operand e1, operand e2)
652 : leunga 815 in doit(opnd1, opnd2)
653 : george 545 end
654 : leunga 815 )
655 : monnier 247
656 : george 545 (* Emit a load instruction; makes sure that the destination
657 :     * is a register
658 :     *)
659 :     fun genLoad(mvOp, ea, mem) =
660 :     dstMustBeReg(fn (_, dst) =>
661 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
662 :    
663 :     (* Generate a zero extended loads *)
664 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
665 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
666 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
667 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
668 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
669 :    
670 :     (* Generate a sign extended loads *)
671 :    
672 :     (* Generate setcc instruction:
673 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
674 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
675 :     * Note that we have to use eax as the destination of the
676 :     * setcc because it only works on the registers
677 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
678 :     * are inaccessible in 32 bit mode.
679 : george 545 *)
680 :     fun setcc(ty, cc, t1, t2, yes, no) =
681 : leunga 583 let val (cc, yes, no) =
682 :     if yes > no then (cc, yes, no)
683 :     else (T.Basis.negateCond cc, no, yes)
684 : george 545 in (* Clear the destination first.
685 :     * This this because stupid SETcc
686 :     * only writes to the low order
687 :     * byte. That's Intel architecture, folks.
688 :     *)
689 : leunga 695 case (yes, no, cc) of
690 :     (1, 0, T.LT) =>
691 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
692 :     in move(tmp, rdOpnd);
693 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
694 :     end
695 :     | (1, 0, T.GT) =>
696 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
697 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
698 :     move(tmp, rdOpnd);
699 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
700 :     end
701 :     | (1, 0, _) => (* normal case *)
702 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
703 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
704 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
705 : leunga 583 move(eax, rdOpnd)
706 :     end
707 : leunga 695 | (C1, C2, _) =>
708 : george 545 (* general case;
709 : leunga 583 * from the Intel optimization guide p3-5
710 :     *)
711 : leunga 695 let val _ = zero eax;
712 :     val cc = cmp(true, ty, cc, t1, t2, [])
713 : leunga 583 in case C1-C2 of
714 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
715 :     let val (base,scale) =
716 :     case D of
717 :     1 => (NONE, 0)
718 :     | 2 => (NONE, 1)
719 :     | 3 => (SOME C.eax, 1)
720 :     | 4 => (NONE, 2)
721 :     | 5 => (SOME C.eax, 2)
722 :     | 8 => (NONE, 3)
723 :     | 9 => (SOME C.eax, 3)
724 :     val addr = I.Indexed{base=base,
725 :     index=C.eax,
726 :     scale=scale,
727 :     disp=I.Immed C2,
728 : george 545 mem=readonly}
729 : leunga 583 val tmpR = newReg()
730 :     val tmp = I.Direct tmpR
731 :     in emit(I.SET{cond=cond cc, opnd=eax});
732 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
733 :     move(tmp, rdOpnd)
734 :     end
735 :     | D =>
736 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
737 :     opnd=eax});
738 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
739 :     emit(I.BINARY{binOp=I.ANDL,
740 :     src=I.Immed D, dst=eax});
741 :     if C2 = 0 then
742 :     move(eax, rdOpnd)
743 :     else
744 :     let val tmpR = newReg()
745 :     val tmp = I.Direct tmpR
746 :     in mark(I.LEA{addr=
747 :     I.Displace{
748 :     base=C.eax,
749 :     disp=I.Immed C2,
750 :     mem=readonly},
751 :     r32=tmpR}, an);
752 :     move(tmp, rdOpnd)
753 :     end
754 :     )
755 :     end
756 : george 545 end (* setcc *)
757 :    
758 :     (* Generate cmovcc instruction.
759 :     * on Pentium Pro and Pentium II only
760 :     *)
761 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
762 :     let fun genCmov(dstR, _) =
763 :     let val _ = doExpr(no, dstR, []) (* false branch *)
764 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
765 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
766 :     end
767 :     in dstMustBeReg genCmov
768 :     end
769 :    
770 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
771 : monnier 247
772 : leunga 606 (* Add n to rd *)
773 :     fun addN n =
774 :     let val n = operand n
775 :     val src = if isMemReg rd then immedOrReg n else n
776 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
777 :    
778 : george 545 (* Generate addition *)
779 :     fun addition(e1, e2) =
780 : leunga 606 case e1 of
781 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e2
782 : leunga 744 else addition1(e1,e2)
783 : leunga 606 | _ => addition1(e1,e2)
784 :     and addition1(e1, e2) =
785 :     case e2 of
786 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e1
787 : leunga 744 else addition2(e1,e2)
788 : leunga 606 | _ => addition2(e1,e2)
789 :     and addition2(e1,e2) =
790 : george 545 (dstMustBeReg(fn (dstR, _) =>
791 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
792 :     handle EA => binaryComm(I.ADDL, e1, e2))
793 : monnier 247
794 :    
795 : george 545 in case exp of
796 :     T.REG(_,rs) =>
797 :     if isMemReg rs andalso isMemReg rd then
798 :     let val tmp = I.Direct(newReg())
799 : leunga 731 in move'(I.MemReg rs, tmp, an);
800 : george 545 move'(tmp, rdOpnd, [])
801 :     end
802 :     else move'(IntReg rs, rdOpnd, an)
803 : george 761 | T.LI z => let
804 :     val n = toInt32 z
805 :     in
806 :     if n=0 then
807 :     (* As per Fermin's request, special optimization for rd := 0.
808 :     * Currently we don't bother with the size.
809 :     *)
810 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
811 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
812 :     else
813 :     move'(I.Immed(n), rdOpnd, an)
814 :     end
815 : leunga 775 | (T.CONST _ | T.LABEL _) =>
816 :     move'(I.ImmedLabel exp, rdOpnd, an)
817 :     | T.LABEXP le => move'(I.ImmedLabel le, rdOpnd, an)
818 : monnier 247
819 : george 545 (* 32-bit addition *)
820 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
821 :     val n = toInt32 n
822 :     in
823 :     case n
824 :     of 1 => unary(I.INCL, e1)
825 :     | ~1 => unary(I.DECL, e1)
826 :     | _ => addition(e1, e2)
827 :     end
828 :     | T.ADD(32, e1 as T.LI n, e2) => let
829 :     val n = toInt32 n
830 :     in
831 :     case n
832 :     of 1 => unary(I.INCL, e2)
833 :     | ~1 => unary(I.DECL, e2)
834 :     | _ => addition(e1, e2)
835 :     end
836 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
837 : monnier 247
838 : leunga 695 (* 32-bit addition but set the flag!
839 :     * This is a stupid hack for now.
840 :     *)
841 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
842 :     val n = T.I.toInt(32, n)
843 :     in
844 :     if n=1 then unary(I.INCL, e)
845 :     else if n = ~1 then unary(I.DECL, e)
846 :     else binaryComm(I.ADDL, e, e1)
847 :     end
848 :     | T.ADD(0, e1 as T.LI n, e) => let
849 :     val n = T.I.toInt(32, n)
850 :     in
851 :     if n=1 then unary(I.INCL, e)
852 :     else if n = ~1 then unary(I.DECL, e)
853 :     else binaryComm(I.ADDL, e1, e)
854 :     end
855 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
856 :    
857 : george 545 (* 32-bit subtraction *)
858 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
859 :     val n = toInt32 n
860 :     in
861 :     case n
862 :     of 0 => doExpr(e1, rd, an)
863 :     | 1 => unary(I.DECL, e1)
864 :     | ~1 => unary(I.INCL, e1)
865 :     | _ => binary(I.SUBL, e1, e2)
866 :     end
867 :     | T.SUB(32, e1 as T.LI n, e2) =>
868 :     if T.I.isZero n then unary(I.NEGL, e2)
869 :     else binary(I.SUBL, e1, e2)
870 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
871 : monnier 247
872 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
873 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
874 :     | T.REMU(32, x, y) => rem(false, false, x, y)
875 : monnier 247
876 : george 545 | T.MULS(32, x, y) => multiply(x, y)
877 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
878 :     | T.REMS(32, x, y) => rem(true, false, x, y)
879 : monnier 247
880 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
881 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
882 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
883 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
884 :     | T.REMT(32, x, y) => rem(true, true, x, y)
885 : monnier 247
886 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
887 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
888 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
889 :     | T.NOTB(32, x) => unary(I.NOTL, x)
890 : monnier 247
891 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
892 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
893 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
894 : monnier 247
895 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
896 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
897 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
898 : monnier 498
899 : leunga 776 | T.SX(32,8,T.LOAD(8,ea,mem)) => load8s(ea, mem)
900 :     | T.SX(32,16,T.LOAD(16,ea,mem)) => load16s(ea, mem)
901 :     | T.ZX(32,8,T.LOAD(8,ea,mem)) => load8(ea, mem)
902 : leunga 779 | T.ZX(32,16,T.LOAD(16,ea,mem)) => load16(ea, mem)
903 : leunga 776
904 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
905 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
906 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
907 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
908 :     Pentium => unknownExp exp
909 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
910 :     )
911 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
912 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
913 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
914 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
915 : george 555 | T.REXT e =>
916 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
917 : george 545 (* simplify and try again *)
918 :     | exp => unknownExp exp
919 :     end (* doExpr *)
920 : monnier 247
921 : george 545 (* generate an expression and return its result register
922 :     * If rewritePseudo is on, the result is guaranteed to be in a
923 :     * non memReg register
924 :     *)
925 :     and expr(exp as T.REG(_, rd)) =
926 :     if isMemReg rd then genExpr exp else rd
927 :     | expr exp = genExpr exp
928 : monnier 247
929 : george 545 and genExpr exp =
930 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
931 : monnier 247
932 : george 545 (* Compare an expression with zero.
933 :     * On the x86, TEST is superior to AND for doing the same thing,
934 :     * since it doesn't need to write out the result in a register.
935 :     *)
936 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
937 : george 545 (case ty of
938 : leunga 695 8 => test(I.TESTB, a, b, an)
939 :     | 16 => test(I.TESTW, a, b, an)
940 :     | 32 => test(I.TESTL, a, b, an)
941 :     | _ => doExpr(e, newReg(), an);
942 :     cc)
943 :     | cmpWithZero(cc, e, an) =
944 :     let val e =
945 :     case e of (* hack to disable the lea optimization XXX *)
946 :     T.ADD(_, a, b) => T.ADD(0, a, b)
947 :     | e => e
948 :     in doExpr(e, newReg(), an); cc end
949 : monnier 247
950 : george 545 (* Emit a test.
951 :     * The available modes are
952 :     * r/m, r
953 :     * r/m, imm
954 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
955 :     * When anding an operand with a constant
956 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
957 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
958 :     * this works for memory operands too. However, with TESTB, it is
959 :     * not possible to use registers other than
960 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
961 :     * perform register allocation first, and if the operand registers
962 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
963 :     * by TESTB.
964 :     *)
965 : leunga 695 and test(testopcode, a, b, an) =
966 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
967 :     (* translate r, r/m => r/m, r *)
968 :     val (opnd1, opnd2) =
969 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
970 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
971 : george 545 end
972 : monnier 247
973 : leunga 815 (* %eflags <- src *)
974 :     and moveToEflags src =
975 : george 889 if CB.sameColor(src, C.eflags) then ()
976 : leunga 815 else (move(I.Direct src, eax); emit(I.LAHF))
977 :    
978 :     (* dst <- %eflags *)
979 :     and moveFromEflags dst =
980 : george 889 if CB.sameColor(dst, C.eflags) then ()
981 : leunga 815 else (emit(I.SAHF); move(eax, I.Direct dst))
982 :    
983 : george 545 (* generate a condition code expression
984 : leunga 744 * The zero is for setting the condition code!
985 :     * I have no idea why this is used.
986 :     *)
987 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
988 : leunga 815 (cmp(false, ty, cc, t1, t2, an);
989 :     moveFromEflags rd
990 :     )
991 :     | doCCexpr(T.CC(cond,rs), rd, an) =
992 : george 889 if CB.sameColor(rs,C.eflags) orelse CB.sameColor(rd,C.eflags) then
993 : leunga 815 (moveToEflags rs; moveFromEflags rd)
994 : leunga 744 else
995 : leunga 815 move'(I.Direct rs, I.Direct rd, an)
996 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
997 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
998 :     | doCCexpr(T.CCEXT e, cd, an) =
999 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
1000 : george 545 | doCCexpr _ = error "doCCexpr"
1001 : monnier 247
1002 : george 545 and ccExpr e = error "ccExpr"
1003 : monnier 247
1004 : george 545 (* generate a comparison and sets the condition code;
1005 :     * return the actual cc used. If the flag swapable is true,
1006 :     * we can also reorder the operands.
1007 :     *)
1008 :     and cmp(swapable, ty, cc, t1, t2, an) =
1009 : leunga 695 (* == and <> can be always be reordered *)
1010 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
1011 :     in (* Sometimes the comparison is not necessary because
1012 :     * the bits are already set!
1013 :     *)
1014 :     if isZero t1 andalso setZeroBit2 t2 then
1015 :     if swapable then
1016 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
1017 :     else (* can't reorder the comparison! *)
1018 :     genCmp(ty, false, cc, t1, t2, an)
1019 :     else if isZero t2 andalso setZeroBit2 t1 then
1020 :     cmpWithZero(cc, t1, an)
1021 :     else genCmp(ty, swapable, cc, t1, t2, an)
1022 :     end
1023 : monnier 247
1024 : george 545 (* Give a and b which are the operands to a comparison (or test)
1025 :     * Return the appropriate condition code and operands.
1026 :     * The available modes are:
1027 :     * r/m, imm
1028 :     * r/m, r
1029 :     * r, r/m
1030 :     *)
1031 :     and commuteComparison(cc, swapable, a, b) =
1032 :     let val (opnd1, opnd2) = (operand a, operand b)
1033 :     in (* Try to fold in the operands whenever possible *)
1034 :     case (isImmediate opnd1, isImmediate opnd2) of
1035 :     (true, true) => (cc, moveToReg opnd1, opnd2)
1036 :     | (true, false) =>
1037 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
1038 :     else (cc, moveToReg opnd1, opnd2)
1039 :     | (false, true) => (cc, opnd1, opnd2)
1040 :     | (false, false) =>
1041 :     (case (opnd1, opnd2) of
1042 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1043 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1044 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1045 :     )
1046 :     end
1047 :    
1048 :     (* generate a real comparison; return the real cc used *)
1049 :     and genCmp(ty, swapable, cc, a, b, an) =
1050 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1051 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1052 :     end
1053 : monnier 247
1054 : george 545 (* generate code for jumps *)
1055 : leunga 775 and jmp(lexp as T.LABEL lab, labs, an) =
1056 : george 545 mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1057 : leunga 775 | jmp(T.LABEXP le, labs, an) = mark(I.JMP(I.ImmedLabel le, labs), an)
1058 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1059 : george 545
1060 :     (* convert mlrisc to cellset:
1061 :     *)
1062 :     and cellset mlrisc =
1063 : jhr 900 let val addCCReg = CB.CellSet.add
1064 : george 545 fun g([],acc) = acc
1065 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1066 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1067 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1068 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1069 :     | g(_::regs, acc) = g(regs, acc)
1070 :     in g(mlrisc, C.empty) end
1071 :    
1072 :     (* generate code for calls *)
1073 : blume 839 and call(ea, flow, def, use, mem, cutsTo, an, pops) =
1074 : leunga 815 let fun return(set, []) = set
1075 :     | return(set, a::an) =
1076 :     case #peek A.RETURN_ARG a of
1077 : jhr 900 SOME r => return(CB.CellSet.add(r, set), an)
1078 : leunga 815 | NONE => return(set, an)
1079 : blume 839 in
1080 :     mark(I.CALL{opnd=operand ea,defs=cellset(def),uses=cellset(use),
1081 :     return=return(C.empty,an),cutsTo=cutsTo,mem=mem,
1082 :     pops=pops},an)
1083 : leunga 815 end
1084 : george 545
1085 : leunga 815 (* generate code for integer stores; first move data to %eax
1086 :     * This is mainly because we can't allocate to registers like
1087 :     * ah, dl, dx etc.
1088 :     *)
1089 :     and genStore(mvOp, ea, d, mem, an) =
1090 :     let val src =
1091 : george 545 case immedOrReg(operand d) of
1092 :     src as I.Direct r =>
1093 : george 889 if CB.sameColor(r,C.eax)
1094 : leunga 744 then src else (move(src, eax); eax)
1095 : george 545 | src => src
1096 : leunga 815 in mark(I.MOVE{mvOp=mvOp, src=src, dst=address(ea,mem)},an)
1097 : george 545 end
1098 : leunga 815
1099 :     (* generate code for 8-bit integer stores *)
1100 :     (* movb has to use %eax as source. Stupid x86! *)
1101 :     and store8(ea, d, mem, an) = genStore(I.MOVB, ea, d, mem, an)
1102 : blume 818 and store16(ea, d, mem, an) =
1103 :     mark(I.MOVE{mvOp=I.MOVW, src=immedOrReg(operand d), dst=address(ea, mem)}, an)
1104 : george 545 and store32(ea, d, mem, an) =
1105 :     move'(immedOrReg(operand d), address(ea, mem), an)
1106 :    
1107 :     (* generate code for branching *)
1108 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1109 :     (* allow reordering of operands *)
1110 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1111 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1112 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1113 :     fbranch(fty, fcc, t1, t2, lab, an)
1114 :     | branch(ccexp, lab, an) =
1115 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1116 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1117 :     )
1118 :    
1119 :     (* generate code for floating point compare and branch *)
1120 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1121 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1122 :     | ignoreOrder (T.FLOAD _) = true
1123 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1124 :     | ignoreOrder _ = false
1125 :    
1126 :     fun compare'() = (* Sethi-Ullman style *)
1127 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1128 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1129 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1130 :     emit(I.FXCH{opnd=C.ST(1)}));
1131 :     emit(I.FUCOMPP);
1132 :     fcc
1133 :     )
1134 :    
1135 :     fun compare''() =
1136 :     (* direct style *)
1137 :     (* Try to make lsrc the memory operand *)
1138 :     let val lsrc = foperand(fty, t1)
1139 :     val rsrc = foperand(fty, t2)
1140 :     val fsize = fsize fty
1141 :     fun cmp(lsrc, rsrc, fcc) =
1142 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1143 :     in case (lsrc, rsrc) of
1144 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1145 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1146 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1147 :     | (lsrc, rsrc) => (* can't be both memory! *)
1148 :     let val ftmpR = newFreg()
1149 :     val ftmp = I.FPR ftmpR
1150 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1151 :     cmp(lsrc, ftmp, fcc)
1152 :     end
1153 :     end
1154 :    
1155 :     fun compare() =
1156 :     if enableFastFPMode andalso !fast_floating_point
1157 :     then compare''() else compare'()
1158 :    
1159 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1160 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1161 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1162 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1163 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1164 :     fun sahf() = emit(I.SAHF)
1165 : leunga 731 fun branch(fcc) =
1166 : george 545 case fcc
1167 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1168 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1169 :     | T.? => (sahf(); j(I.P,lab))
1170 :     | T.<=> => (sahf(); j(I.NP,lab))
1171 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1172 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1173 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1174 :     | T.?< => (testil 0x500; j(I.NE,lab))
1175 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1176 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1177 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1178 :     cmpil 0x4000; j(I.EQ,lab))
1179 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1180 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1181 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1182 : jhr 1119 | _ => error(concat[
1183 :     "fbranch(", T.Basis.fcondToString fcc, ")"
1184 :     ])
1185 : george 545 (*esac*)
1186 : leunga 731 val fcc = compare()
1187 :     in emit I.FNSTSW;
1188 :     branch(fcc)
1189 : monnier 411 end
1190 : monnier 247
1191 : leunga 731 (*========================================================
1192 :     * Floating point code generation starts here.
1193 :     * Some generic fp routines first.
1194 :     *========================================================*)
1195 :    
1196 :     (* Can this tree be folded into the src operand of a floating point
1197 :     * operations?
1198 :     *)
1199 :     and foldableFexp(T.FREG _) = true
1200 :     | foldableFexp(T.FLOAD _) = true
1201 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1202 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1203 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1204 :     | foldableFexp _ = false
1205 :    
1206 :     (* Move integer e of size ty into a memory location.
1207 :     * Returns a quadruple:
1208 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1209 :     *)
1210 :     and convertIntToFloat(ty, e) =
1211 :     let val opnd = operand e
1212 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1213 :     then (INTEGER, ty, opnd, [])
1214 :     else
1215 : leunga 815 let val {instrs, tempMem, cleanup} =
1216 :     cvti2f{ty=ty, src=opnd, an=getAnnotations()}
1217 : leunga 731 in emits instrs;
1218 :     (INTEGER, 32, tempMem, cleanup)
1219 :     end
1220 :     end
1221 :    
1222 :     (*========================================================
1223 :     * Sethi-Ullman based floating point code generation as
1224 :     * implemented by Lal
1225 :     *========================================================*)
1226 :    
1227 : george 545 and fld(32, opnd) = I.FLDS opnd
1228 :     | fld(64, opnd) = I.FLDL opnd
1229 : george 555 | fld(80, opnd) = I.FLDT opnd
1230 : george 545 | fld _ = error "fld"
1231 :    
1232 : leunga 565 and fild(16, opnd) = I.FILD opnd
1233 :     | fild(32, opnd) = I.FILDL opnd
1234 :     | fild(64, opnd) = I.FILDLL opnd
1235 :     | fild _ = error "fild"
1236 :    
1237 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1238 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1239 :    
1240 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1241 :     | fstp(64, opnd) = I.FSTPL opnd
1242 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1243 : george 545 | fstp _ = error "fstp"
1244 :    
1245 :     (* generate code for floating point stores *)
1246 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1247 : george 545 (case d of
1248 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1249 :     | _ => reduceFexp(fty, d, []);
1250 :     mark(fstp(fty, address(ea, mem)), an)
1251 :     )
1252 :    
1253 : leunga 731 (* generate code for floating point loads *)
1254 :     and fload'(fty, ea, mem, fd, an) =
1255 :     let val ea = address(ea, mem)
1256 :     in mark(fld(fty, ea), an);
1257 : george 889 if CB.sameColor(fd,ST0) then ()
1258 : leunga 744 else emit(fstp(fty, I.FDirect fd))
1259 : leunga 731 end
1260 :    
1261 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1262 : george 545
1263 :     (* generate floating point expression and put the result in fd *)
1264 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1265 : george 889 (if CB.sameColor(fs,fd) then ()
1266 : george 1009 else mark'(I.COPY{k=CB.FP, sz=64, dst=[fd], src=[fs], tmp=NONE}, an)
1267 : george 545 )
1268 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1269 :     fload'(fty, ea, mem, fd, an)
1270 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1271 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1272 : george 889 if CB.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1273 : leunga 731 )
1274 :     | doFexpr'(fty, e, fd, an) =
1275 : george 545 (reduceFexp(fty, e, []);
1276 : george 889 if CB.sameColor(fd,ST0) then ()
1277 : leunga 744 else mark(fstp(fty, I.FDirect fd), an)
1278 : george 545 )
1279 :    
1280 :     (*
1281 :     * Generate floating point expression using Sethi-Ullman's scheme:
1282 :     * This function evaluates a floating point expression,
1283 :     * and put result in %ST(0).
1284 :     *)
1285 :     and reduceFexp(fty, fexp, an) =
1286 : george 555 let val ST = I.ST(C.ST 0)
1287 :     val ST1 = I.ST(C.ST 1)
1288 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1289 : george 545
1290 : leunga 565 datatype su_tree =
1291 :     LEAF of int * T.fexp * ans
1292 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1293 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1294 :     and fbinop = FADD | FSUB | FMUL | FDIV
1295 :     | FIADD | FISUB | FIMUL | FIDIV
1296 :     withtype ans = Annotations.annotations
1297 : monnier 247
1298 : leunga 565 fun label(LEAF(n, _, _)) = n
1299 :     | label(BINARY(n, _, _, _, _, _)) = n
1300 :     | label(UNARY(n, _, _, _, _)) = n
1301 : george 545
1302 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1303 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1304 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1305 : george 545
1306 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1307 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1308 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1309 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1310 :     | su(T.CVTF2F(_, _, t)) = su t
1311 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1312 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1313 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1314 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1315 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1316 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1317 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1318 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1319 :     | su _ = error "su"
1320 :    
1321 :     (* Try to fold the the memory operand or integer conversion *)
1322 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1323 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1324 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1325 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1326 :     | suFold(T.FMARK(t, a)) =
1327 :     let val (t, integer) = suFold t
1328 :     in (annotate(t, a), integer) end
1329 :     | suFold e = (su e, false)
1330 :    
1331 :     (* Form unary tree *)
1332 :     and suUnary(fty, funary, t) =
1333 :     let val t = su t
1334 :     in UNARY(label t, fty, funary, t, [])
1335 : george 545 end
1336 : leunga 565
1337 :     (* Form binary tree *)
1338 :     and suBinary(fty, binop, ibinop, t1, t2) =
1339 :     let val t1 = su t1
1340 :     val (t2, integer) = suFold t2
1341 :     val n1 = label t1
1342 :     val n2 = label t2
1343 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1344 :     val myOp = if integer then ibinop else binop
1345 :     in BINARY(n, fty, myOp, t1, t2, [])
1346 : george 545 end
1347 : george 555
1348 : leunga 565 (* Try to fold in the operand if possible.
1349 :     * This only applies to commutative operations.
1350 :     *)
1351 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1352 : leunga 731 let val (t1, t2) = if foldableFexp t2
1353 :     then (t1, t2) else (t2, t1)
1354 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1355 :    
1356 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1357 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1358 : george 889 t1 = t2 andalso CB.sameColor(f1,f2)
1359 : leunga 565 | sameTree _ = false
1360 :    
1361 :     (* Traverse tree and generate code *)
1362 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1363 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1364 :     let val _ = gencode x
1365 :     val (_, fty, src) = leafEA y
1366 :     fun gen(code) = mark(code, a1 @ a2)
1367 :     fun binary(oper32, oper64) =
1368 :     if sameTree(x, t2) then
1369 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1370 : george 555 else
1371 :     let val oper =
1372 : leunga 565 if isMemOpnd src then
1373 :     case fty of
1374 :     32 => oper32
1375 :     | 64 => oper64
1376 :     | _ => error "gencode: BINARY"
1377 :     else oper64
1378 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1379 :     fun ibinary(oper16, oper32) =
1380 :     let val oper = case fty of
1381 :     16 => oper16
1382 :     | 32 => oper32
1383 :     | _ => error "gencode: IBINARY"
1384 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1385 :     in case binop of
1386 :     FADD => binary(I.FADDS, I.FADDL)
1387 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1388 :     | FMUL => binary(I.FMULS, I.FMULL)
1389 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1390 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1391 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1392 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1393 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1394 :     end
1395 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1396 :     let fun doit(t1, t2, oper, operP, operRP) =
1397 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1398 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1399 :     *)
1400 :     val n1 = label t1
1401 :     val n2 = label t2
1402 :     in if n1 < n2 andalso n1 <= 7 then
1403 :     (gencode t2;
1404 :     gencode t1;
1405 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1406 :     else if n2 <= n1 andalso n2 <= 7 then
1407 :     (gencode t1;
1408 :     gencode t2;
1409 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1410 :     else
1411 :     let (* both labels > 7 *)
1412 :     val fs = I.FDirect(newFreg())
1413 :     in gencode t2;
1414 :     emit(fstp(fty, fs));
1415 :     gencode t1;
1416 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1417 :     end
1418 :     end
1419 :     in case binop of
1420 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1421 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1422 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1423 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1424 : george 545 | _ => error "gencode.BINARY"
1425 :     end
1426 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1427 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1428 :    
1429 :     (* Generate code for a leaf.
1430 :     * Returns the type and an effective address
1431 :     *)
1432 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1433 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1434 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1435 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1436 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1437 : leunga 565 | leafEA _ = error "leafEA"
1438 :    
1439 : leunga 731 and int2real(ty, e) =
1440 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1441 :     in cleanupCode := !cleanupCode @ cleanup;
1442 :     (INTEGER, ty, ea)
1443 : george 545 end
1444 : leunga 731
1445 :     in gencode(su fexp);
1446 :     emits(!cleanupCode)
1447 : george 545 end (*reduceFexp*)
1448 : leunga 731
1449 :     (*========================================================
1450 :     * This section generates 3-address style floating
1451 :     * point code.
1452 :     *========================================================*)
1453 :    
1454 :     and isize 16 = I.I16
1455 :     | isize 32 = I.I32
1456 :     | isize _ = error "isize"
1457 :    
1458 :     and fstore''(fty, ea, d, mem, an) =
1459 :     (floatingPointUsed := true;
1460 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1461 :     src=foperand(fty, d)},
1462 :     an)
1463 :     )
1464 :    
1465 :     and fload''(fty, ea, mem, d, an) =
1466 :     (floatingPointUsed := true;
1467 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1468 :     dst=RealReg d}, an)
1469 :     )
1470 :    
1471 :     and fiload''(ity, ea, d, an) =
1472 :     (floatingPointUsed := true;
1473 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1474 :     )
1475 :    
1476 :     and fexpr''(e as T.FREG(_,f)) =
1477 :     if isFMemReg f then transFexpr e else f
1478 :     | fexpr'' e = transFexpr e
1479 :    
1480 :     and transFexpr e =
1481 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1482 :    
1483 :     (*
1484 :     * Process a floating point operand. Put operand in register
1485 :     * when possible. The operand should match the given fty.
1486 :     *)
1487 :     and foperand(fty, e as T.FREG(fty', f)) =
1488 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1489 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1490 :     foperand(fty, e) (* nop on the x86 *)
1491 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1492 :     (* fold operand when the precison matches *)
1493 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1494 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1495 :    
1496 :     (*
1497 :     * Process a floating point operand.
1498 :     * Try to fold in a memory operand or conversion from an integer.
1499 :     *)
1500 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1501 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1502 :     (REAL, fty, address(ea, mem), [])
1503 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1504 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1505 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1506 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1507 :    
1508 :     (* Generate binary operator. Since the real binary operators
1509 :     * does not take memory as destination, we also ensure this
1510 :     * does not happen.
1511 :     *)
1512 :     and fbinop(targetFty,
1513 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1514 :     (* Put the mem operand in rsrc *)
1515 :     let val _ = floatingPointUsed := true;
1516 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1517 :     | isMemOpnd(T.FLOAD _) = true
1518 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1519 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1520 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1521 :     | isMemOpnd _ = false
1522 :     val (binOp, ibinOp, lsrc, rsrc) =
1523 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1524 :     else (binOp, ibinOp, lsrc, rsrc)
1525 :     val lsrc = foperand(targetFty, lsrc)
1526 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1527 :     fun dstMustBeFreg f =
1528 :     if targetFty <> 64 then
1529 :     let val tmpR = newFreg()
1530 :     val tmp = I.FPR tmpR
1531 :     in mark(f tmp, an);
1532 :     emit(I.FMOVE{fsize=fsize targetFty,
1533 :     src=tmp, dst=RealReg fd})
1534 :     end
1535 :     else mark(f(RealReg fd), an)
1536 :     in case kind of
1537 :     REAL =>
1538 :     dstMustBeFreg(fn dst =>
1539 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1540 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1541 :     | INTEGER =>
1542 :     (dstMustBeFreg(fn dst =>
1543 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1544 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1545 :     emits code
1546 :     )
1547 :     end
1548 : george 545
1549 : leunga 731 and funop(fty, unOp, src, fd, an) =
1550 :     let val src = foperand(fty, src)
1551 :     in mark(I.FUNOP{fsize=fsize fty,
1552 :     unOp=unOp, src=src, dst=RealReg fd},an)
1553 :     end
1554 :    
1555 :     and doFexpr''(fty, e, fd, an) =
1556 :     case e of
1557 : george 889 T.FREG(_,fs) => if CB.sameColor(fs,fd) then ()
1558 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1559 :     (* Stupid x86 does everything as 80-bits internally. *)
1560 :    
1561 :     (* Binary operators *)
1562 :     | T.FADD(_, a, b) => fbinop(fty,
1563 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1564 :     a, b, fd, an)
1565 :     | T.FSUB(_, a, b) => fbinop(fty,
1566 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1567 :     a, b, fd, an)
1568 :     | T.FMUL(_, a, b) => fbinop(fty,
1569 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1570 :     a, b, fd, an)
1571 :     | T.FDIV(_, a, b) => fbinop(fty,
1572 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1573 :     a, b, fd, an)
1574 :    
1575 :     (* Unary operators *)
1576 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1577 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1578 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1579 :    
1580 :     (* Load *)
1581 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1582 :    
1583 :     (* Type conversions *)
1584 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1585 :     | T.CVTI2F(_, ty, e) =>
1586 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1587 :     in fiload''(ty, ea, fd, an);
1588 :     emits cleanup
1589 :     end
1590 :    
1591 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1592 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1593 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1594 :     | T.FEXT fexp =>
1595 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1596 :     | _ => error("doFexpr''")
1597 :    
1598 :     (*========================================================
1599 :     * Tie the two styles of fp code generation together
1600 :     *========================================================*)
1601 :     and fstore(fty, ea, d, mem, an) =
1602 :     if enableFastFPMode andalso !fast_floating_point
1603 :     then fstore''(fty, ea, d, mem, an)
1604 :     else fstore'(fty, ea, d, mem, an)
1605 :     and fload(fty, ea, d, mem, an) =
1606 :     if enableFastFPMode andalso !fast_floating_point
1607 :     then fload''(fty, ea, d, mem, an)
1608 :     else fload'(fty, ea, d, mem, an)
1609 :     and fexpr e =
1610 :     if enableFastFPMode andalso !fast_floating_point
1611 :     then fexpr'' e else fexpr' e
1612 :     and doFexpr(fty, e, fd, an) =
1613 :     if enableFastFPMode andalso !fast_floating_point
1614 :     then doFexpr''(fty, e, fd, an)
1615 :     else doFexpr'(fty, e, fd, an)
1616 :    
1617 : leunga 797 (*================================================================
1618 :     * Optimizations for x := x op y
1619 :     * Special optimizations:
1620 :     * Generate a binary operator, result must in memory.
1621 :     * The source must not be in memory
1622 :     *================================================================*)
1623 :     and binaryMem(binOp, src, dst, mem, an) =
1624 :     mark(I.BINARY{binOp=binOp, src=immedOrReg(operand src),
1625 :     dst=address(dst,mem)}, an)
1626 :     and unaryMem(unOp, opnd, mem, an) =
1627 :     mark(I.UNARY{unOp=unOp, opnd=address(opnd,mem)}, an)
1628 :    
1629 :     and isOne(T.LI n) = n = one
1630 :     | isOne _ = false
1631 :    
1632 :     (*
1633 :     * Perform optimizations based on recognizing
1634 :     * x := x op y or
1635 :     * x := y op x
1636 :     * first.
1637 :     *)
1638 :     and store(ty, ea, d, mem, an,
1639 :     {INC,DEC,ADD,SUB,NOT,NEG,SHL,SHR,SAR,OR,AND,XOR},
1640 :     doStore
1641 :     ) =
1642 :     let fun default() = doStore(ea, d, mem, an)
1643 :     fun binary1(t, t', unary, binary, ea', x) =
1644 :     if t = ty andalso t' = ty then
1645 :     if MLTreeUtils.eqRexp(ea, ea') then
1646 :     if isOne x then unaryMem(unary, ea, mem, an)
1647 :     else binaryMem(binary, x, ea, mem, an)
1648 :     else default()
1649 :     else default()
1650 :     fun unary(t,unOp, ea') =
1651 :     if t = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1652 :     unaryMem(unOp, ea, mem, an)
1653 :     else default()
1654 :     fun binary(t,t',binOp,ea',x) =
1655 :     if t = ty andalso t' = ty andalso
1656 :     MLTreeUtils.eqRexp(ea, ea') then
1657 :     binaryMem(binOp, x, ea, mem, an)
1658 :     else default()
1659 :    
1660 :     fun binaryCom1(t,unOp,binOp,x,y) =
1661 :     if t = ty then
1662 :     let fun again() =
1663 :     case y of
1664 :     T.LOAD(ty',ea',_) =>
1665 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1666 :     if isOne x then unaryMem(unOp, ea, mem, an)
1667 :     else binaryMem(binOp,x,ea,mem,an)
1668 :     else default()
1669 :     | _ => default()
1670 :     in case x of
1671 :     T.LOAD(ty',ea',_) =>
1672 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1673 :     if isOne y then unaryMem(unOp, ea, mem, an)
1674 :     else binaryMem(binOp,y,ea,mem,an)
1675 :     else again()
1676 :     | _ => again()
1677 :     end
1678 :     else default()
1679 :    
1680 :     fun binaryCom(t,binOp,x,y) =
1681 :     if t = ty then
1682 :     let fun again() =
1683 :     case y of
1684 :     T.LOAD(ty',ea',_) =>
1685 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1686 :     binaryMem(binOp,x,ea,mem,an)
1687 :     else default()
1688 :     | _ => default()
1689 :     in case x of
1690 :     T.LOAD(ty',ea',_) =>
1691 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1692 :     binaryMem(binOp,y,ea,mem,an)
1693 :     else again()
1694 :     | _ => again()
1695 :     end
1696 :     else default()
1697 :    
1698 :     in case d of
1699 :     T.ADD(t,x,y) => binaryCom1(t,INC,ADD,x,y)
1700 :     | T.SUB(t,T.LOAD(t',ea',_),x) => binary1(t,t',DEC,SUB,ea',x)
1701 :     | T.ORB(t,x,y) => binaryCom(t,OR,x,y)
1702 :     | T.ANDB(t,x,y) => binaryCom(t,AND,x,y)
1703 :     | T.XORB(t,x,y) => binaryCom(t,XOR,x,y)
1704 :     | T.SLL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHL,ea',x)
1705 :     | T.SRL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHR,ea',x)
1706 :     | T.SRA(t,T.LOAD(t',ea',_),x) => binary(t,t',SAR,ea',x)
1707 :     | T.NEG(t,T.LOAD(t',ea',_)) => unary(t,NEG,ea')
1708 :     | T.NOTB(t,T.LOAD(t',ea',_)) => unary(t,NOT,ea')
1709 :     | _ => default()
1710 :     end (* store *)
1711 :    
1712 : george 545 (* generate code for a statement *)
1713 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1714 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1715 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1716 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1717 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1718 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1719 : blume 839 | stmt(T.CALL{funct, targets, defs, uses, region, pops, ...}, an) =
1720 :     call(funct,targets,defs,uses,region,[],an, pops)
1721 :     | stmt(T.FLOW_TO(T.CALL{funct, targets, defs, uses, region, pops, ...},
1722 : leunga 796 cutTo), an) =
1723 : blume 839 call(funct,targets,defs,uses,region,cutTo,an, pops)
1724 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1725 : leunga 797 | stmt(T.STORE(8, ea, d, mem), an) =
1726 :     store(8, ea, d, mem, an, opcodes8, store8)
1727 :     | stmt(T.STORE(16, ea, d, mem), an) =
1728 :     store(16, ea, d, mem, an, opcodes16, store16)
1729 :     | stmt(T.STORE(32, ea, d, mem), an) =
1730 :     store(32, ea, d, mem, an, opcodes32, store32)
1731 :    
1732 : george 545 | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1733 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1734 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1735 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1736 : george 555 | stmt(T.EXT s, an) =
1737 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1738 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1739 :    
1740 :     and doStmt s = stmt(s, [])
1741 :     and doStmts ss = app doStmt ss
1742 :    
1743 :     and beginCluster' _ =
1744 :     ((* Must be cleared by the client.
1745 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1746 :     *)
1747 : leunga 731 floatingPointUsed := false;
1748 :     trapLabel := NONE;
1749 :     beginCluster 0
1750 :     )
1751 : george 545 and endCluster' a =
1752 : monnier 247 (case !trapLabel
1753 : monnier 411 of NONE => ()
1754 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1755 : monnier 411 (*esac*);
1756 : leunga 731 (* If floating point has been used allocate an extra
1757 :     * register just in case we didn't use any explicit register
1758 :     *)
1759 :     if !floatingPointUsed then (newFreg(); ())
1760 :     else ();
1761 : george 545 endCluster(a)
1762 :     )
1763 :    
1764 :     and reducer() =
1765 : george 984 TS.REDUCER{reduceRexp = expr,
1766 : george 545 reduceFexp = fexpr,
1767 :     reduceCCexp = ccExpr,
1768 :     reduceStm = stmt,
1769 :     operand = operand,
1770 :     reduceOperand = reduceOpnd,
1771 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1772 : george 1009 emit = mark',
1773 : george 545 instrStream = instrStream,
1774 :     mltreeStream = self()
1775 :     }
1776 :    
1777 :     and self() =
1778 : george 984 TS.S.STREAM
1779 : leunga 815 { beginCluster = beginCluster',
1780 :     endCluster = endCluster',
1781 :     emit = doStmt,
1782 :     pseudoOp = pseudoOp,
1783 :     defineLabel = defineLabel,
1784 :     entryLabel = entryLabel,
1785 :     comment = comment,
1786 :     annotation = annotation,
1787 :     getAnnotations = getAnnotations,
1788 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1789 : george 545 }
1790 :    
1791 :     in self()
1792 : monnier 247 end
1793 :    
1794 : george 545 end (* functor *)
1795 :    
1796 :     end (* local *)

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