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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : monnier 247 (* X86.sml -- pattern matching version of x86 instruction set generation.
2 :     *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 :     * -- Allen
26 : monnier 247 *)
27 : george 545 local
28 :     val rewriteMemReg = true (* should we rewrite memRegs *)
29 :     in
30 :    
31 : monnier 247 functor X86
32 :     (structure X86Instr : X86INSTR
33 :     structure X86MLTree : MLTREE
34 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
35 :     where I = X86Instr and T = X86MLTree
36 : monnier 475 sharing X86MLTree.Region = X86Instr.Region
37 : george 545 sharing X86MLTree.LabelExp = X86Instr.LabelExp
38 :     datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
39 :     val arch : arch ref
40 :     val tempMem : X86Instr.operand (* temporary for CVTI2F *)
41 :     ) : sig include MLTREECOMP
42 :     val rewriteMemReg : bool
43 :     end =
44 : monnier 247 struct
45 :     structure T = X86MLTree
46 : monnier 429 structure S = T.Stream
47 : monnier 247 structure I = X86Instr
48 : george 545 structure C = I.C
49 :     structure Shuffle = Shuffle(I)
50 : monnier 247 structure W32 = Word32
51 : george 545 structure LE = I.LabelExp
52 :     structure A = MLRiscAnnotations
53 : monnier 247
54 : george 545 type instrStream = (I.instruction,C.regmap,C.cellset) T.stream
55 : george 555 type mltreeStream = (T.stm,C.regmap,T.mlrisc list) T.stream
56 : george 545
57 :     structure Gen = MLTreeGen
58 :     (structure T = T
59 :     val intTy = 32
60 :     val naturalWidths = [32]
61 :     datatype rep = SE | ZE | NEITHER
62 :     val rep = NEITHER
63 :     )
64 :    
65 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
66 : monnier 247
67 : george 545 (* Should we perform automatic MemReg translation?
68 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
69 :     *)
70 :     val rewriteMemReg = rewriteMemReg
71 :     fun isMemReg r = rewriteMemReg andalso r >= 8 andalso r < 32
72 : monnier 247
73 : george 555 val ST0 = C.ST 0
74 :     val ST7 = C.ST 7
75 :    
76 : george 545 (*
77 :     * The code generator
78 :     *)
79 : monnier 411 fun selectInstructions
80 : george 545 (instrStream as
81 :     S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,
82 : monnier 429 beginCluster,endCluster,exitBlock,alias,phi,comment,...}) =
83 : george 545 let exception EA
84 : monnier 411
85 : george 545 (* label where a trap is generated -- one per cluster *)
86 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
87 : monnier 247
88 : george 545 (* effective address of an integer register *)
89 :     fun IntReg r = if isMemReg r then MemReg r else I.Direct r
90 :     and MemReg r =
91 :     ((* memRegsUsed := Word.orb(!memRegsUsed,
92 :     Word.<<(0w1, Word.fromInt r-0w8)); *)
93 :     I.MemReg r
94 :     )
95 : monnier 411
96 : george 545 (* Add an overflow trap *)
97 :     fun trap() =
98 :     let val jmp =
99 :     case !trapLabel of
100 :     NONE => let val label = Label.newLabel "trap"
101 :     val jmp = I.JCC{cond=I.O,
102 :     opnd=I.ImmedLabel(LE.LABEL label)}
103 :     in trapLabel := SOME(jmp, label); jmp end
104 :     | SOME(jmp, _) => jmp
105 :     in emit jmp end
106 : monnier 411
107 : george 545 val newReg = C.newReg
108 :     val newFreg = C.newFreg
109 : monnier 247
110 : george 545 (* mark an expression with a list of annotations *)
111 :     fun mark'(i,[]) = i
112 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
113 : monnier 247
114 : george 545 (* annotate an expression and emit it *)
115 :     fun mark(i,an) = emit(mark'(i,an))
116 : monnier 247
117 : george 545 (* emit parallel copies for integers
118 :     * Translates parallel copies that involve memregs into
119 :     * individual copies.
120 :     *)
121 :     fun copy([], [], an) = ()
122 :     | copy(dst, src, an) =
123 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
124 :     if rd = rs then [] else
125 :     let val tmpR = I.Direct(newReg())
126 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
127 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
128 :     end
129 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
130 :     if rd = rs then []
131 :     else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
132 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
133 :     in
134 :     app emit (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
135 :     {regmap=fn r => r, tmp=SOME(I.Direct(newReg())),
136 :     dst=dst, src=src})
137 :     end
138 :    
139 :     (* conversions *)
140 :     val itow = Word.fromInt
141 :     val wtoi = Word.toInt
142 :     fun toInt32 i = Int32.fromLarge(Int.toLarge i)
143 :     val w32toi32 = Word32.toLargeIntX
144 :     val i32tow32 = Word32.fromLargeInt
145 : monnier 247
146 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
147 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
148 : monnier 247
149 : george 545 (* some useful registers *)
150 :     val eax = I.Direct(C.eax)
151 :     val ecx = I.Direct(C.ecx)
152 :     val edx = I.Direct(C.edx)
153 : monnier 247
154 : george 545 fun immedLabel lab = I.ImmedLabel(LE.LABEL lab)
155 :    
156 :     (* Is the expression zero? *)
157 :     fun isZero(T.LI 0) = true
158 :     | isZero(T.LI32 0w0) = true
159 :     | isZero(T.MARK(e,a)) = isZero e
160 :     | isZero _ = false
161 :     (* Does the expression set the zero bit?
162 :     * WARNING: we assume these things are not optimized out!
163 :     *)
164 :     fun setZeroBit(T.ANDB _) = true
165 :     | setZeroBit(T.ORB _) = true
166 :     | setZeroBit(T.XORB _) = true
167 :     | setZeroBit(T.SRA _) = true
168 :     | setZeroBit(T.SRL _) = true
169 :     | setZeroBit(T.SLL _) = true
170 :     | setZeroBit(T.MARK(e, _)) = setZeroBit e
171 :     | setZeroBit _ = false
172 : monnier 247
173 : george 545 (* emit parallel copies for floating point *)
174 :     fun fcopy(fty, [], [], _) = ()
175 :     | fcopy(fty, dst as [_], src as [_], an) =
176 :     mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
177 :     | fcopy(fty, dst, src, an) =
178 :     mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
179 : monnier 247
180 : george 545 (* Translates MLTREE condition code to x86 condition code *)
181 :     fun cond T.LT = I.LT | cond T.LTU = I.B
182 :     | cond T.LE = I.LE | cond T.LEU = I.BE
183 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
184 :     | cond T.GE = I.GE | cond T.GEU = I.AE
185 :     | cond T.GT = I.GT | cond T.GTU = I.A
186 : monnier 247
187 : george 545 (* Move and annotate *)
188 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
189 :     if s=d then ()
190 :     else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
191 :     | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
192 : monnier 247
193 : george 545 (* Move only! *)
194 :     fun move(src, dst) = move'(src, dst, [])
195 : monnier 247
196 : george 545 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
197 : monnier 247
198 : george 545 val readonly = I.Region.readonly
199 : monnier 247
200 : george 545 (*
201 :     * Compute an effective address. This is a new version
202 :     *)
203 :     fun address(ea, mem) =
204 :     let (* tricky way to negate without overflow! *)
205 :     fun neg32 w = Word32.notb w + 0w1
206 : monnier 247
207 : george 545 (* Keep building a bigger and bigger effective address expressions
208 :     * The input is a list of trees
209 :     * b -- base
210 :     * i -- index
211 :     * s -- scale
212 :     * d -- immed displacement
213 :     *)
214 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
215 :     | doEA(t::trees, b, i, s, d) =
216 :     (case t of
217 :     T.LI n => doEAImmed(trees, n, b, i, s, d)
218 :     | T.LI32 n => doEAImmedw(trees, n, b, i, s, d)
219 :     | T.CONST c => doEALabel(trees, LE.CONST c, b, i, s, d)
220 :     | T.LABEL le => doEALabel(trees, le, b, i, s, d)
221 :     | T.ADD(32, t1, t2 as T.REG(_,r)) =>
222 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
223 :     else doEA(t1::t2::trees, b, i, s, d)
224 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
225 :     | T.SUB(32, t1, T.LI n) =>
226 :     (* can't overflow here *)
227 :     doEA(t1::T.LI32(neg32(Word32.fromInt n))::trees, b, i, s, d)
228 :     | T.SUB(32, t1, T.LI32 n) =>
229 :     doEA(t1::T.LI32(neg32 n)::trees, b, i, s, d)
230 :     | T.SLL(32, t1, T.LI 0) => displace(trees, t1, b, i, s, d)
231 :     | T.SLL(32, t1, T.LI 1) => indexed(trees, t1, t, 1, b, i, s, d)
232 :     | T.SLL(32, t1, T.LI 2) => indexed(trees, t1, t, 2, b, i, s, d)
233 :     | T.SLL(32, t1, T.LI 3) => indexed(trees, t1, t, 3, b, i, s, d)
234 :     | T.SLL(32, t1, T.LI32 0w0) => displace(trees, t1, b, i, s, d)
235 :     | T.SLL(32, t1, T.LI32 0w1) => indexed(trees,t1,t,1,b,i,s,d)
236 :     | T.SLL(32, t1, T.LI32 0w2) => indexed(trees,t1,t,2,b,i,s,d)
237 :     | T.SLL(32, t1, T.LI32 0w3) => indexed(trees,t1,t,3,b,i,s,d)
238 :     | t => displace(trees, t, b, i, s, d)
239 :     )
240 : monnier 247
241 : george 545 (* Add an immed constant *)
242 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
243 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
244 :     doEA(trees, b, i, s, (* no overflow! *)
245 :     I.Immed(w32toi32(Word32.fromInt n + i32tow32 m)))
246 :     | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
247 :     doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,LE.INT n)))
248 :     | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
249 : monnier 247
250 : george 545 (* Add an immed32 constant *)
251 :     and doEAImmedw(trees, 0w0, b, i, s, d) = doEA(trees, b, i, s, d)
252 :     | doEAImmedw(trees, n, b, i, s, I.Immed m) =
253 :     (* no overflow! *)
254 :     doEA(trees, b, i, s, I.Immed(w32toi32(i32tow32 m + n)))
255 :     | doEAImmedw(trees, n, b, i, s, I.ImmedLabel le) =
256 :     doEA(trees, b, i, s,
257 :     I.ImmedLabel(LE.PLUS(le,LE.INT(Word32.toIntX n)))
258 :     handle Overflow => error "doEAImmedw: constant too large")
259 :     | doEAImmedw(trees, n, b, i, s, _) = error "doEAImmedw"
260 : monnier 247
261 : george 545 (* Add a label expression *)
262 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
263 :     doEA(trees, b, i, s, I.ImmedLabel le)
264 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
265 :     doEA(trees, b, i, s,
266 :     I.ImmedLabel(LE.PLUS(le,LE.INT(Int32.toInt m)))
267 :     handle Overflow => error "doEALabel: constant too large")
268 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
269 :     doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,le')))
270 :     | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
271 : monnier 247
272 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
273 :     | makeAddressingMode(SOME base, NONE, _, disp) =
274 :     I.Displace{base=base, disp=disp, mem=mem}
275 :     | makeAddressingMode(base, SOME index, scale, disp) =
276 :     I.Indexed{base=base, index=index, scale=scale,
277 :     disp=disp, mem=mem}
278 : monnier 247
279 : george 545 (* generate code for tree and ensure that it is not in %esp *)
280 :     and exprNotEsp tree =
281 :     let val r = expr tree
282 :     in if r = C.esp then
283 :     let val tmp = newReg()
284 :     in move(I.Direct r, I.Direct tmp); tmp end
285 :     else r
286 :     end
287 : monnier 247
288 : george 545 (* Add a base register *)
289 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
290 :     doEA(trees, SOME(expr t), i, s, d)
291 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
292 :     (* make t the index, but make sure that it is not %esp! *)
293 :     let val i = expr t
294 :     in if i = C.esp then
295 :     (* swap base and index *)
296 :     if base <> C.esp then
297 :     doEA(trees, SOME i, b, 0, d)
298 :     else (* base and index = %esp! *)
299 :     let val index = newReg()
300 :     in move(I.Direct i, I.Direct index);
301 :     doEA(trees, b, SOME index, 0, d)
302 :     end
303 :     else
304 :     doEA(trees, b, SOME i, 0, d)
305 :     end
306 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
307 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
308 :     in doEA(trees, SOME b, i, s, d) end
309 : monnier 247
310 : george 545 (* Add an indexed register *)
311 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
312 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
313 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
314 :     doEA(trees, SOME(expr t0), i, s, d)
315 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
316 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
317 :     in doEA(trees, SOME b, i, s, d) end
318 :    
319 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
320 :     I.Immed _ => raise EA
321 :     | I.ImmedLabel le => I.LabelEA le
322 :     | ea => ea
323 :     end (* address *)
324 : monnier 247
325 : george 545 (* reduce an expression into an operand *)
326 :     and operand(T.LI i) = I.Immed(toInt32 i)
327 :     | operand(T.LI32 w) = I.Immed(wToInt32 w)
328 :     | operand(T.CONST c) = I.ImmedLabel(LE.CONST c)
329 :     | operand(T.LABEL lab) = I.ImmedLabel lab
330 :     | operand(T.REG(_,r)) = IntReg r
331 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
332 :     | operand(t) = I.Direct(expr t)
333 : monnier 247
334 : george 545 and moveToReg(opnd) =
335 :     let val dst = I.Direct(newReg())
336 :     in move(opnd, dst); dst
337 :     end
338 : monnier 247
339 : george 545 and reduceOpnd(I.Direct r) = r
340 :     | reduceOpnd opnd =
341 :     let val dst = newReg()
342 :     in move(opnd, I.Direct dst); dst
343 :     end
344 : monnier 247
345 : george 545 (* ensure that the operand is either an immed or register *)
346 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
347 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
348 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
349 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
350 :     | immedOrReg opnd = opnd
351 : monnier 247
352 : george 545 and isImmediate(I.Immed _) = true
353 :     | isImmediate(I.ImmedLabel _) = true
354 :     | isImmediate _ = false
355 : monnier 247
356 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
357 :    
358 :     and isMemOpnd opnd =
359 :     (case opnd of
360 :     I.Displace _ => true
361 :     | I.Indexed _ => true
362 :     | I.MemReg _ => true
363 :     | I.LabelEA _ => true
364 : george 555 | I.FDirect f => true
365 : george 545 | _ => false
366 :     )
367 :    
368 :     (*
369 :     * Compute an integer expression and put the result in
370 :     * the destination register rd.
371 :     *)
372 :     and doExpr(exp, rd : I.C.cell, an) =
373 :     let val rdOpnd = IntReg rd
374 : monnier 247
375 : george 545 fun equalRd(I.Direct r) = r = rd
376 :     | equalRd(I.MemReg r) = r = rd
377 :     | equalRd _ = false
378 : monnier 247
379 : george 545 (* Emit a binary operator. If the destination is
380 :     * a memReg, do something smarter.
381 :     *)
382 :     fun genBinary(binOp, opnd1, opnd2) =
383 :     if isMemReg rd andalso
384 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
385 :     equalRd(opnd2)
386 :     then
387 :     let val tmpR = newReg()
388 :     val tmp = I.Direct tmpR
389 :     in move(opnd1, tmp);
390 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
391 :     move(tmp, rdOpnd)
392 :     end
393 :     else
394 :     (move(opnd1, rdOpnd);
395 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
396 :     )
397 : monnier 247
398 : george 545 (* Generate a binary operator; it may commute *)
399 :     fun binaryComm(binOp, e1, e2) =
400 :     let val (opnd1, opnd2) =
401 :     case (operand e1, operand e2) of
402 :     (x as I.Immed _, y) => (y, x)
403 :     | (x as I.ImmedLabel _, y) => (y, x)
404 :     | (x, y as I.Direct _) => (y, x)
405 :     | (x, y) => (x, y)
406 :     in genBinary(binOp, opnd1, opnd2)
407 :     end
408 :    
409 :     (* Generate a binary operator; non-commutative *)
410 :     fun binary(binOp, e1, e2) =
411 :     genBinary(binOp, operand e1, operand e2)
412 :    
413 :     (* Generate a unary operator *)
414 :     fun unary(unOp, e) =
415 :     let val opnd = operand e
416 :     in if isMemReg rd andalso isMemOpnd opnd then
417 :     let val tmp = I.Direct(newReg())
418 :     in move(opnd, tmp); move(tmp, rdOpnd)
419 :     end
420 :     else move(opnd, rdOpnd);
421 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
422 :     end
423 :    
424 :     (* Generate shifts; the shift
425 :     * amount must be a constant or in %ecx *)
426 :     fun shift(opcode, e1, e2) =
427 :     let val (opnd1, opnd2) = (operand e1, operand e2)
428 :     in case opnd2 of
429 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
430 :     | _ =>
431 :     if equalRd(opnd2) then
432 :     let val tmpR = newReg()
433 :     val tmp = I.Direct tmpR
434 :     in move(opnd1, tmp);
435 :     move(opnd2, ecx);
436 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
437 :     move(tmp, rdOpnd)
438 :     end
439 :     else
440 :     (move(opnd1, rdOpnd);
441 :     move(opnd2, ecx);
442 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
443 :     )
444 :     end
445 :    
446 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
447 :     fun divrem(signed, overflow, e1, e2, resultReg) =
448 :     let val (opnd1, opnd2) = (operand e1, operand e2)
449 :     val _ = move(opnd1, eax)
450 :     val oper = if signed then (emit(I.CDQ); I.IDIV)
451 :     else (zero edx; I.UDIV)
452 :     in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
453 :     move(resultReg, rdOpnd);
454 :     if overflow then trap() else ()
455 :     end
456 :    
457 :     (* Optimize the special case for division *)
458 :     fun divide(signed, overflow, e1, e2 as T.LI n) =
459 :     let fun isPowerOf2 w = Word.andb((w - 0w1), w) = 0w0
460 :     fun log2 n = (* n must be > 0!!! *)
461 :     let fun loop(0w1,pow) = pow
462 :     | loop(w,pow) = loop(Word.>>(w, 0w1),pow+1)
463 :     in loop(n,0) end
464 :     val w = Word.fromInt n
465 :     in if n > 1 andalso isPowerOf2 w then
466 :     let val pow = T.LI(log2 w)
467 :     in if signed then
468 :     (* signed; simulate round towards zero *)
469 :     let val label = Label.newLabel ""
470 :     val reg1 = expr e1
471 :     val opnd1 = I.Direct reg1
472 :     in if setZeroBit e1 then ()
473 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
474 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
475 :     emit(if n = 2 then
476 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
477 :     else
478 :     I.BINARY{binOp=I.ADDL,
479 :     src=I.Immed(toInt32 n - 1),
480 :     dst=opnd1});
481 :     defineLabel label;
482 :     shift(I.SARL, T.REG(32, reg1), pow)
483 :     end
484 :     else (* unsigned *)
485 :     shift(I.SHRL, e1, pow)
486 :     end
487 :     else
488 :     (* note the only way we can overflow is if
489 :     * n = 0 or n = -1
490 :     *)
491 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
492 :     e1, e2, eax)
493 :     end
494 :     | divide(signed, overflow, e1, e2) =
495 :     divrem(signed, overflow, e1, e2, eax)
496 : monnier 247
497 : george 545 fun rem(signed, overflow, e1, e2) =
498 :     divrem(signed, overflow, e1, e2, edx)
499 :    
500 :     (* unsigned integer multiplication *)
501 :     fun uMultiply(e1, e2) =
502 :     (* note e2 can never be (I.Direct edx) *)
503 :     (move(operand e1, eax);
504 :     mark(I.MULTDIV{multDivOp=I.UMUL,
505 :     src=regOrMem(operand e2)},an);
506 :     move(eax, rdOpnd)
507 :     )
508 :    
509 :     (* signed integer multiplication:
510 :     * The only forms that are allowed that also sets the
511 :     * OF and CF flags are:
512 :     *
513 :     * imul r32, r32/m32, imm8
514 :     * imul r32, imm8
515 :     * imul r32, imm32
516 :     *)
517 :     fun multiply(e1, e2) =
518 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _, dstR, dst) =
519 :     (move(i1, dst);
520 :     mark(I.MUL3{dst=dstR, src1=i2, src2=NONE},an))
521 :     | doit(rm, i2 as I.Immed _, dstR, dst) =
522 :     doit(i2, rm, dstR, dst)
523 :     | doit(imm as I.Immed(i), rm, dstR, dst) =
524 :     mark(I.MUL3{dst=dstR, src1=rm, src2=SOME i},an)
525 :     | doit(r1 as I.Direct _, r2 as I.Direct _, dstR, dst) =
526 :     (move(r1, dst);
527 :     mark(I.MUL3{dst=dstR, src1=r2, src2=NONE},an))
528 :     | doit(r1 as I.Direct _, rm, dstR, dst) =
529 :     (move(r1, dst);
530 :     mark(I.MUL3{dst=dstR, src1=rm, src2=NONE},an))
531 :     | doit(rm, r as I.Direct _, dstR, dst) =
532 :     doit(r, rm, dstR, dst)
533 :     | doit(rm1, rm2, dstR, dst) =
534 :     if equalRd rm2 then
535 :     let val tmpR = newReg()
536 :     val tmp = I.Direct tmpR
537 :     in move(rm1, tmp);
538 :     mark(I.MUL3{dst=tmpR, src1=rm2, src2=NONE},an);
539 :     move(tmp, dst)
540 :     end
541 :     else
542 :     (move(rm1, dst);
543 :     mark(I.MUL3{dst=dstR, src1=rm2, src2=NONE},an)
544 :     )
545 :     val (opnd1, opnd2) = (operand e1, operand e2)
546 :     in if isMemReg rd then (* destination must be a real reg *)
547 :     let val tmpR = newReg()
548 :     val tmp = I.Direct tmpR
549 :     in doit(opnd1, opnd2, tmpR, tmp);
550 :     move(tmp, rdOpnd)
551 :     end
552 :     else
553 :     doit(opnd1, opnd2, rd, rdOpnd)
554 :     end
555 : monnier 247
556 : george 545 (* Makes sure the destination must be a register *)
557 :     fun dstMustBeReg f =
558 :     if isMemReg rd then
559 :     let val tmpR = newReg()
560 :     val tmp = I.Direct(tmpR)
561 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
562 :     else f(rd, rdOpnd)
563 : monnier 247
564 : george 545 (* Emit a load instruction; makes sure that the destination
565 :     * is a register
566 :     *)
567 :     fun genLoad(mvOp, ea, mem) =
568 :     dstMustBeReg(fn (_, dst) =>
569 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
570 :    
571 :     (* Generate a zero extended loads *)
572 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
573 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
574 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
575 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
576 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
577 :    
578 :     (* Generate a sign extended loads *)
579 :    
580 :     (* Generate setcc instruction:
581 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
582 :     *)
583 :     fun setcc(ty, cc, t1, t2, yes, no) =
584 :     let val tmpR = newReg()
585 :     val tmp = I.Direct tmpR
586 :     (* We create a temporary here just in
587 :     * case t1 or t2 contains a use of rd.
588 :     *)
589 :     in (* Clear the destination first.
590 :     * This this because stupid SETcc
591 :     * only writes to the low order
592 :     * byte. That's Intel architecture, folks.
593 :     *)
594 :     zero tmp;
595 :     case (yes, no) of
596 :     (1, 0) => (* normal case *)
597 :     let val cc = cmp(true, ty, cc, t1, t2, [])
598 :     in mark(I.SET{cond=cond cc, opnd=tmp}, an) end
599 :     | (0, 1) => (* flip *)
600 :     let val cc = cmp(true, ty,
601 :     T.Basis.negateCond cc, t1, t2, [])
602 :     in mark(I.SET{cond=cond cc, opnd=tmp}, an) end
603 :     | (C1, C2) =>
604 :     (* general case;
605 :     * from the Intel optimization guide p3-5 *)
606 :     let val C1 = toInt32 C1
607 :     val C2 = toInt32 C2
608 :     val cc = cmp(true, ty, cc, t1, t2, [])
609 :     in emit(I.SET{cond=cond cc, opnd=tmp});
610 :     case Int32.abs(C1-C2)-1 of
611 :     D as (1 | 2 | 4 | 8) =>
612 :     let val addr = I.Indexed{base=SOME tmpR,
613 :     index=tmpR,
614 :     scale=Int32.toInt D,
615 :     disp=I.Immed(C1-C2),
616 :     mem=readonly}
617 :     in mark(I.LEA{r32=tmpR, addr=addr}, an) end
618 :     | _ =>
619 :     (emit(I.UNARY{unOp=I.DECL, opnd=tmp});
620 :     emit(I.BINARY{binOp=I.ANDL,
621 :     src=I.Immed(C2-C1), dst=tmp});
622 :     mark(I.BINARY{binOp=I.ADDL,
623 :     src=I.Immed(Int32.min(C1,C2)),
624 :     dst=tmp}, an)
625 :     )
626 :     end;
627 :     move(tmp, rdOpnd)
628 :     end (* setcc *)
629 :    
630 :     (* Generate cmovcc instruction.
631 :     * on Pentium Pro and Pentium II only
632 :     *)
633 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
634 :     let fun genCmov(dstR, _) =
635 :     let val _ = doExpr(no, dstR, []) (* false branch *)
636 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
637 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
638 :     end
639 :     in dstMustBeReg genCmov
640 :     end
641 :    
642 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
643 : monnier 247
644 : george 545 (* Generate addition *)
645 :     fun addition(e1, e2) =
646 :     (dstMustBeReg(fn (dstR, _) =>
647 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
648 :     handle EA => binaryComm(I.ADDL, e1, e2))
649 : monnier 247
650 : george 545 (* Add n to rd *)
651 :     fun addN n =
652 :     mark(I.BINARY{binOp=I.ADDL, src=I.Immed(toInt32 n),
653 :     dst=rdOpnd}, an)
654 : monnier 247
655 : george 545 in case exp of
656 :     T.REG(_,rs) =>
657 :     if isMemReg rs andalso isMemReg rd then
658 :     let val tmp = I.Direct(newReg())
659 :     in move'(MemReg rs, tmp, an);
660 :     move'(tmp, rdOpnd, [])
661 :     end
662 :     else move'(IntReg rs, rdOpnd, an)
663 :     | (T.LI 0 | T.LI32 0w0) =>
664 :     (* As per Fermin's request, special optimization for rd := 0.
665 :     * Currently we don't bother with the size.
666 :     *)
667 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
668 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
669 :     | T.LI n => move'(I.Immed(toInt32 n), rdOpnd, an)
670 :     | T.LI32 w => move'(I.Immed(wToInt32 w), rdOpnd, an)
671 :     | T.CONST c => move'(I.ImmedLabel(LE.CONST c), rdOpnd, an)
672 :     | T.LABEL lab => move'(I.ImmedLabel lab, rdOpnd, an)
673 : monnier 247
674 : george 545 (* 32-bit addition *)
675 :     | T.ADD(32, e, (T.LI 1|T.LI32 0w1)) => unary(I.INCL, e)
676 :     | T.ADD(32, (T.LI 1|T.LI32 0w1), e) => unary(I.INCL, e)
677 :     | T.ADD(32, e, T.LI ~1) => unary(I.DECL, e)
678 :     | T.ADD(32, T.LI ~1, e) => unary(I.DECL, e)
679 :     | T.ADD(32, e1 as T.REG(_, rs), e2 as T.LI n) =>
680 :     if rs = rd then addN n else addition(e1, e2)
681 :     | T.ADD(32, e1 as T.LI n, e2 as T.REG(_, rs)) =>
682 :     if rs = rd then addN n else addition(e1, e2)
683 :     | T.ADD(32, e1, e2) => addition(e1, e2)
684 : monnier 247
685 : george 545 (* 32-bit subtraction *)
686 :     | T.SUB(32, e, (T.LI 1 | T.LI32 0w1)) => unary(I.DECL, e)
687 :     | T.SUB(32, e, T.LI ~1) => unary(I.INCL, e)
688 :     | T.SUB(32, (T.LI 0 | T.LI32 0w0), e) => unary(I.NEGL, e)
689 : monnier 247
690 : george 545 (* Never mind:
691 :     | T.SUB(32, e1, e2 as T.LI n) =>
692 :     (mark(I.LEA{r32=rd, addr=address(T.ADD(32, e1, T.LI(~n)),
693 :     I.Region.readonly)}, an)
694 :     handle (Overflow|EA) => binary(I.SUBL, e1, e2))
695 :     *)
696 :     | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
697 : monnier 247
698 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
699 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
700 :     | T.REMU(32, x, y) => rem(false, false, x, y)
701 : monnier 247
702 : george 545 | T.MULS(32, x, y) => multiply(x, y)
703 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
704 :     | T.REMS(32, x, y) => rem(true, false, x, y)
705 : monnier 247
706 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
707 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
708 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
709 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
710 :     | T.REMT(32, x, y) => rem(true, true, x, y)
711 : monnier 247
712 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
713 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
714 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
715 :     | T.NOTB(32, x) => unary(I.NOTL, x)
716 : monnier 247
717 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
718 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
719 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
720 : monnier 247
721 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
722 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
723 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
724 :     | T.CVTI2I(_,T.SIGN_EXTEND,_,T.LOAD(8,ea,mem)) => load8s(ea, mem)
725 :     | T.CVTI2I(_,T.SIGN_EXTEND,_,T.LOAD(16,ea,mem)) => load16s(ea, mem)
726 : monnier 498
727 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
728 :     setcc(ty, cc, t1, t2, yes, no)
729 :     | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
730 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
731 :     Pentium => unknownExp exp
732 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
733 :     )
734 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
735 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
736 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
737 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
738 : george 555 | T.REXT e =>
739 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
740 : george 545 (* simplify and try again *)
741 :     | exp => unknownExp exp
742 :     end (* doExpr *)
743 : monnier 247
744 : george 545 (* generate an expression and return its result register
745 :     * If rewritePseudo is on, the result is guaranteed to be in a
746 :     * non memReg register
747 :     *)
748 :     and expr(exp as T.REG(_, rd)) =
749 :     if isMemReg rd then genExpr exp else rd
750 :     | expr exp = genExpr exp
751 : monnier 247
752 : george 545 and genExpr exp =
753 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
754 : monnier 247
755 : george 545 (* Compare an expression with zero.
756 :     * On the x86, TEST is superior to AND for doing the same thing,
757 :     * since it doesn't need to write out the result in a register.
758 :     *)
759 :     and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b)) =
760 :     (case ty of
761 :     8 => test(I.TESTB, a, b)
762 :     | 16 => test(I.TESTW, a, b)
763 :     | 32 => test(I.TESTL, a, b)
764 :     | _ => (expr e; ())
765 :     ; cc)
766 :     | cmpWithZero(cc, e) = (expr e; cc)
767 : monnier 247
768 : george 545 (* Emit a test.
769 :     * The available modes are
770 :     * r/m, r
771 :     * r/m, imm
772 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
773 :     * When anding an operand with a constant
774 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
775 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
776 :     * this works for memory operands too. However, with TESTB, it is
777 :     * not possible to use registers other than
778 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
779 :     * perform register allocation first, and if the operand registers
780 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
781 :     * by TESTB.
782 :     *)
783 :     and test(testopcode, a, b) =
784 :     let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
785 :     (* translate r, r/m => r/m, r *)
786 :     val (opnd1, opnd2) =
787 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
788 :     in emit(testopcode{lsrc=opnd1, rsrc=opnd2})
789 :     end
790 : monnier 247
791 : george 545 (* generate a condition code expression
792 :     * The zero is for setting the condition code!
793 :     * I have no idea why this is used.
794 :     *)
795 :     and doCCexpr(T.CMP(ty, cc, t1, t2), 0, an) =
796 :     (cmp(false, ty, cc, t1, t2, an); ())
797 :     | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
798 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
799 :     | doCCexpr(T.CCEXT e, cd, an) =
800 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
801 : george 545 | doCCexpr _ = error "doCCexpr"
802 : monnier 247
803 : george 545 and ccExpr e = error "ccExpr"
804 : monnier 247
805 : george 545 (* generate a comparison and sets the condition code;
806 :     * return the actual cc used. If the flag swapable is true,
807 :     * we can also reorder the operands.
808 :     *)
809 :     and cmp(swapable, ty, cc, t1, t2, an) =
810 :     (case cc of
811 :     (T.EQ | T.NE) =>
812 :     (* Sometimes the comparison is not necessary because
813 :     * the bits are already set!
814 :     *)
815 :     if isZero t1 andalso setZeroBit t2 then cmpWithZero(cc, t2)
816 :     else if isZero t2 andalso setZeroBit t1 then cmpWithZero(cc, t1)
817 :     (* == and <> can be reordered *)
818 :     else genCmp(ty, true, cc, t1, t2, an)
819 :     | _ => genCmp(ty, swapable, cc, t1, t2, an)
820 :     )
821 : monnier 247
822 : george 545 (* Give a and b which are the operands to a comparison (or test)
823 :     * Return the appropriate condition code and operands.
824 :     * The available modes are:
825 :     * r/m, imm
826 :     * r/m, r
827 :     * r, r/m
828 :     *)
829 :     and commuteComparison(cc, swapable, a, b) =
830 :     let val (opnd1, opnd2) = (operand a, operand b)
831 :     in (* Try to fold in the operands whenever possible *)
832 :     case (isImmediate opnd1, isImmediate opnd2) of
833 :     (true, true) => (cc, moveToReg opnd1, opnd2)
834 :     | (true, false) =>
835 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
836 :     else (cc, moveToReg opnd1, opnd2)
837 :     | (false, true) => (cc, opnd1, opnd2)
838 :     | (false, false) =>
839 :     (case (opnd1, opnd2) of
840 :     (_, I.Direct _) => (cc, opnd1, opnd2)
841 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
842 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
843 :     )
844 :     end
845 :    
846 :     (* generate a real comparison; return the real cc used *)
847 :     and genCmp(ty, swapable, cc, a, b, an) =
848 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
849 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
850 :     end
851 : monnier 247
852 : george 545 (* generate code for jumps *)
853 :     and jmp(T.LABEL(lexp as LE.LABEL lab), labs, an) =
854 :     mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
855 :     | jmp(T.LABEL lexp, labs, an) = mark(I.JMP(I.ImmedLabel lexp, labs), an)
856 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
857 :    
858 :     (* convert mlrisc to cellset:
859 :     *)
860 :     and cellset mlrisc =
861 :     let val addCCReg = C.addCell C.CC
862 :     fun g([],acc) = acc
863 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
864 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
865 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
866 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
867 :     | g(_::regs, acc) = g(regs, acc)
868 :     in g(mlrisc, C.empty) end
869 :    
870 :     (* generate code for calls *)
871 :     and call(ea, flow, def, use, mem, an) =
872 :     mark(I.CALL(operand ea,cellset(def),cellset(use),mem),an)
873 :    
874 :     (* generate code for integer stores *)
875 :     and store8(ea, d, mem, an) =
876 :     let val src = (* movb has to use %eax as source. Stupid x86! *)
877 :     case immedOrReg(operand d) of
878 :     src as I.Direct r =>
879 :     if r = C.eax then src else (move(src, eax); eax)
880 :     | src => src
881 :     in mark(I.MOVE{mvOp=I.MOVB, src=src, dst=address(ea,mem)},an)
882 :     end
883 :     and store16(ea, d, mem, an) = error "store16"
884 :     and store32(ea, d, mem, an) =
885 :     move'(immedOrReg(operand d), address(ea, mem), an)
886 :    
887 :     (* generate code for branching *)
888 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
889 :     (* allow reordering of operands *)
890 :     let val cc = cmp(true, ty, cc, t1, t2, [])
891 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
892 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
893 :     fbranch(fty, fcc, t1, t2, lab, an)
894 :     | branch(ccexp, lab, an) =
895 :     (doCCexpr(ccexp, 0, []);
896 :     mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
897 :     )
898 :    
899 :     (* generate code for floating point compare and branch *)
900 :     and fbranch(fty, fcc, t1, t2, lab, an) =
901 :     let fun compare() =
902 :     let fun ignoreOrder (T.FREG _) = true
903 :     | ignoreOrder (T.FLOAD _) = true
904 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
905 :     | ignoreOrder _ = false
906 :     in if ignoreOrder t1 orelse ignoreOrder t2 then
907 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
908 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
909 :     emit(I.FXCH{opnd=C.ST(1)}));
910 :     emit(I.FUCOMPP)
911 : monnier 411 end
912 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
913 :     fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
914 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
915 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
916 :     fun sahf() = emit(I.SAHF)
917 :     fun branch() =
918 :     case fcc
919 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
920 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
921 :     | T.? => (sahf(); j(I.P,lab))
922 :     | T.<=> => (sahf(); j(I.NP,lab))
923 :     | T.> => (andil 0x4500; j(I.EQ,lab))
924 :     | T.?<= => (andil 0x4500; j(I.NE,lab))
925 :     | T.>= => (andil 0x500; j(I.EQ,lab))
926 :     | T.?< => (andil 0x500; j(I.NE,lab))
927 :     | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
928 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
929 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
930 :     cmpil 0x4000; j(I.EQ,lab))
931 :     | T.?> => (sahf(); j(I.P,lab); andil 0x4100; j(I.EQ,lab))
932 :     | T.<> => (andil 0x4400; j(I.EQ,lab))
933 :     | T.?= => (andil 0x4400; j(I.NE,lab))
934 :     | _ => error "fbranch"
935 :     (*esac*)
936 :     in compare(); emit I.FNSTSW; branch()
937 : monnier 411 end
938 : monnier 247
939 : george 545 and fld(32, opnd) = I.FLDS opnd
940 :     | fld(64, opnd) = I.FLDL opnd
941 : george 555 | fld(80, opnd) = I.FLDT opnd
942 : george 545 | fld _ = error "fld"
943 :    
944 :     and fstp(32, opnd) = I.FSTPS opnd
945 :     | fstp(64, opnd) = I.FSTPL opnd
946 : george 555 | fstp(80, opnd) = I.FSTPT opnd
947 : george 545 | fstp _ = error "fstp"
948 :    
949 :     (* generate code for floating point stores *)
950 :     and fstore(fty, ea, d, mem, an) =
951 :     (case d of
952 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
953 :     | _ => reduceFexp(fty, d, []);
954 :     mark(fstp(fty, address(ea, mem)), an)
955 :     )
956 :    
957 :     and fexpr e = error "fexpr"
958 :    
959 :     (* generate floating point expression and put the result in fd *)
960 :     and doFexpr(fty, T.FREG(_, fs), fd, an) =
961 :     (if fs = fd then ()
962 :     else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
963 :     )
964 :     | doFexpr(fty, T.FLOAD(fty', ea, mem), fd, an) =
965 :     let val ea = address(ea, mem)
966 :     in mark(fld(fty', ea), an);
967 :     emit(fstp(fty, I.FDirect fd))
968 :     end
969 :     | doFexpr(fty, e, fd, an) =
970 :     (reduceFexp(fty, e, []);
971 :     mark(fstp(fty, I.FDirect fd), an)
972 :     )
973 :    
974 :     (*
975 :     * Generate floating point expression using Sethi-Ullman's scheme:
976 :     * This function evaluates a floating point expression,
977 :     * and put result in %ST(0).
978 :     *)
979 :     and reduceFexp(fty, fexp, an) =
980 : george 555 let val ST = I.ST(C.ST 0)
981 :     val ST1 = I.ST(C.ST 1)
982 : george 545
983 :     datatype su_numbers =
984 :     LEAF of int
985 :     | BINARY of int * su_numbers * su_numbers
986 :     | UNARY of int * su_numbers
987 : monnier 247
988 : george 545 datatype direction = LEFT | RIGHT
989 :    
990 :     fun label(LEAF n) = n
991 :     | label(BINARY(n, _, _)) = n
992 :     | label(UNARY(n, _)) = n
993 :    
994 :     (* Generate tree of sethi-ullman numbers *)
995 :     fun suBinary(t1, t2) =
996 :     let val su1 = suNumbering(t1, LEFT)
997 :     val su2 = suNumbering(t2, RIGHT)
998 :     val n1 = label su1
999 :     val n2 = label su2
1000 :     in BINARY(if n1=n2 then n1+1 else Int.max(n1, n2), su1, su2)
1001 :     end
1002 :    
1003 :     and suUnary(t) =
1004 :     let val su = suNumbering(t, LEFT)
1005 :     in UNARY(label su, su)
1006 :     end
1007 :    
1008 :     and suNumbering(T.FREG _, LEFT) = LEAF 1
1009 :     | suNumbering(T.FREG _, RIGHT) = LEAF 0
1010 :     | suNumbering(T.FLOAD _, LEFT) = LEAF 1
1011 :     | suNumbering(T.FLOAD _, RIGHT) = LEAF 0
1012 :     | suNumbering(T.FADD(_, t1, t2), _) = suBinary(t1, t2)
1013 :     | suNumbering(T.FMUL(_, t1, t2), _) = suBinary(t1, t2)
1014 :     | suNumbering(T.FSUB(_, t1, t2), _) = suBinary(t1, t2)
1015 :     | suNumbering(T.FDIV(_, t1, t2), _) = suBinary(t1, t2)
1016 :     | suNumbering(T.FABS(_,t), _) = suUnary(t)
1017 :     | suNumbering(T.FNEG(_,t), _) = suUnary(t)
1018 :     | suNumbering(T.CVTI2F _, _) = UNARY(1, LEAF 0)
1019 : george 555 | suNumbering(T.CVTF2F(_,_,T.FLOAD _), _) = UNARY(1, LEAF 0)
1020 : george 545 | suNumbering(T.CVTF2F(_,_,t), _) = suUnary t
1021 :     | suNumbering(T.FMARK(e,a),x) = suNumbering(e,x)
1022 :     | suNumbering _ = error "suNumbering"
1023 :    
1024 :     fun leafEA(T.FREG(fty, f)) = (fty, I.FDirect f)
1025 :     | leafEA(T.FLOAD(fty, ea, mem)) = (fty, address(ea, mem))
1026 : george 555 | leafEA(T.CVTF2F(_, _, T.FLOAD(fty, ea, mem))) =
1027 :     (fty, address(ea, mem))
1028 : george 545 | leafEA _ = error "leafEA"
1029 :    
1030 :     fun cvti2d(t,an) =
1031 :     let val opnd = operand t
1032 :     fun doMemOpnd () =
1033 :     (emit(I.MOVE{mvOp=I.MOVL, src=opnd, dst=tempMem});
1034 :     mark(I.FILD tempMem,an))
1035 :     in case opnd of
1036 :     I.Direct _ => doMemOpnd()
1037 :     | I.Immed _ => doMemOpnd()
1038 :     | _ => mark(I.FILD opnd, an)
1039 :     end
1040 :    
1041 :     (* traverse expression and su-number tree *)
1042 :     fun gencode(_, LEAF 0, an) = ()
1043 :     | gencode(T.FMARK(e,a), x, an) = gencode(e, x, a::an)
1044 :     | gencode(f, LEAF 1, an) = mark(fld(leafEA f), an)
1045 :     | gencode(t, BINARY(_, su1, LEAF 0), an) =
1046 :     let (* optimize the common case when both operands
1047 :     * are equal *)
1048 :     fun sameEA(T.FREG(t1, f1), T.FREG(t2, f2)) =
1049 :     t1 = t2 andalso f1 = f2
1050 :     | sameEA _ = false
1051 : george 555
1052 :     fun doit(oper32, oper64, t1, t2) =
1053 :     let val _ = gencode(t1, su1, [])
1054 :     val (fty, src) = leafEA t2
1055 :     in if sameEA(t1, t2) then
1056 :     mark(I.FBINARY{binOp=oper64, src=ST, dst=ST}, an)
1057 :     else
1058 :     let val oper =
1059 :     if isMemOpnd src then
1060 :     case fty of
1061 :     32 => oper32
1062 :     | 64 => oper64
1063 :     | _ => error "gencode: binary"
1064 :     else oper64
1065 :     in mark(I.FBINARY{binOp=oper, src=src, dst=ST}, an)
1066 :     end
1067 :     end
1068 : george 545 in
1069 :     case t of
1070 : george 555 T.FADD(_, t1, t2) => doit(I.FADDS,I.FADDL,t1,t2)
1071 :     | T.FMUL(_, t1, t2) => doit(I.FMULS,I.FMULL,t1,t2)
1072 :     | T.FSUB(_, t1, t2) => doit(I.FSUBS,I.FSUBL,t1,t2)
1073 :     | T.FDIV(_, t1, t2) => doit(I.FDIVS,I.FDIVL,t1,t2)
1074 : george 545 | _ => error "gencode.BINARY"
1075 :     end
1076 :     | gencode(fexp, BINARY(fty, su1, su2), an) =
1077 :     let fun doit(t1, t2, oper, operP, operRP) = let
1078 :     (* oper[P] => ST(1) := ST oper ST(1); [pop]
1079 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1080 :     *)
1081 :     val n1 = label su1
1082 :     val n2 = label su2
1083 :     in
1084 :     if n1 < n2 andalso n1 <= 7 then
1085 :     (gencode(t2, su2, []);
1086 :     gencode(t1, su1, []);
1087 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1088 :     else if n2 <= n1 andalso n2 <= 7 then
1089 :     (gencode(t1, su1, []);
1090 :     gencode(t2, su2, []);
1091 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1092 :     else let (* both labels > 7 *)
1093 :     val fs = I.FDirect(newFreg())
1094 :     in
1095 :     gencode (t2, su2, []);
1096 :     emit(fstp(fty, fs));
1097 :     gencode (t1, su1, []);
1098 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1099 :     end
1100 :     end
1101 :     in
1102 :     case fexp
1103 : george 555 of T.FADD(_, t1, t2) => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1104 :     | T.FMUL(_, t1, t2) => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1105 :     | T.FSUB(_, t1, t2) => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1106 :     | T.FDIV(_, t1, t2) => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1107 : george 545 | _ => error "gencode.BINARY"
1108 :     end
1109 :     | gencode(fexp, UNARY(_, LEAF 0), an) =
1110 :     (case fexp
1111 :     of T.FABS(fty, t) =>
1112 :     (emit(fld(leafEA t)); mark(I.FUNARY(I.FABS),an))
1113 :     | T.FNEG(fty, t) =>
1114 :     (emit(fld(leafEA t)); mark(I.FUNARY(I.FCHS),an))
1115 :     | T.CVTI2F(_,_,t) => cvti2d(t,an) (* XXX *)
1116 :     | _ => error "gencode.UNARY"
1117 :     (*esac*))
1118 :     | gencode(fexp, UNARY(_, su), an) =
1119 :     let fun doit(oper, t) =
1120 :     (gencode(t, su, []); mark(I.FUNARY(oper),an))
1121 :     in case fexp
1122 :     of T.FABS(_, t) => doit(I.FABS, t)
1123 :     | T.FNEG(_, t) => doit(I.FCHS, t)
1124 :     | T.CVTF2F(_,_,t) => gencode(t, su, an)
1125 :     | T.CVTI2F _ => error "gencode:UNARY:cvti2f"
1126 :     | _ => error "gencode.UNARY"
1127 :     end
1128 :     | gencode _ = error "gencode"
1129 :    
1130 :     val labels = suNumbering(fexp, LEFT)
1131 :     in gencode(fexp, labels, an)
1132 :     end (*reduceFexp*)
1133 :    
1134 :     (* generate code for a statement *)
1135 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1136 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1137 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1138 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1139 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1140 :     | stmt(T.JMP(ctrl, e, labs), an) = jmp(e, labs, an)
1141 :     | stmt(T.CALL(e, flow, def, use, cdef, cuse, mem), an) =
1142 :     call(e,flow,def,use,mem,an)
1143 :     | stmt(T.RET _, an) = mark(I.RET NONE, an)
1144 :     | stmt(T.STORE(8, ea, d, mem), an) = store8(ea, d, mem, an)
1145 :     | stmt(T.STORE(16, ea, d, mem), an) = store16(ea, d, mem, an)
1146 :     | stmt(T.STORE(32, ea, d, mem), an) = store32(ea, d, mem, an)
1147 :     | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1148 :     | stmt(T.BCC(ctrl, cc, lab), an) = branch(cc, lab, an)
1149 :     | stmt(T.DEFINE l, _) = defineLabel l
1150 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1151 : george 555 | stmt(T.EXT s, an) =
1152 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1153 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1154 :    
1155 :     and doStmt s = stmt(s, [])
1156 :     and doStmts ss = app doStmt ss
1157 :    
1158 :     and beginCluster' _ =
1159 :     ((* Must be cleared by the client.
1160 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1161 :     *)
1162 :     trapLabel := NONE; beginCluster 0)
1163 :     and endCluster' a =
1164 : monnier 247 (case !trapLabel
1165 : monnier 411 of NONE => ()
1166 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1167 : monnier 411 (*esac*);
1168 : george 545 endCluster(a)
1169 :     )
1170 :    
1171 :     and reducer() =
1172 :     T.REDUCER{reduceRexp = expr,
1173 :     reduceFexp = fexpr,
1174 :     reduceCCexp = ccExpr,
1175 :     reduceStm = stmt,
1176 :     operand = operand,
1177 :     reduceOperand = reduceOpnd,
1178 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1179 :     emit = mark,
1180 :     instrStream = instrStream,
1181 :     mltreeStream = self()
1182 :     }
1183 :    
1184 :     and self() =
1185 :     S.STREAM
1186 :     { beginCluster= beginCluster',
1187 :     endCluster = endCluster',
1188 :     emit = doStmt,
1189 :     pseudoOp = pseudoOp,
1190 :     defineLabel = defineLabel,
1191 :     entryLabel = entryLabel,
1192 :     comment = comment,
1193 :     annotation = annotation,
1194 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc),
1195 :     alias = alias,
1196 :     phi = phi
1197 :     }
1198 :    
1199 :     in self()
1200 : monnier 247 end
1201 :    
1202 : george 545 end (* functor *)
1203 :    
1204 :     end (* local *)

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