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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 :     * -- Allen
26 : monnier 247 *)
27 : george 545 local
28 :     val rewriteMemReg = true (* should we rewrite memRegs *)
29 :     in
30 :    
31 : monnier 247 functor X86
32 :     (structure X86Instr : X86INSTR
33 :     structure X86MLTree : MLTREE
34 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
35 :     where I = X86Instr and T = X86MLTree
36 : monnier 475 sharing X86MLTree.Region = X86Instr.Region
37 : george 545 sharing X86MLTree.LabelExp = X86Instr.LabelExp
38 :     datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
39 :     val arch : arch ref
40 : leunga 593 val cvti2f :
41 :     (* source operand, guaranteed to be non-memory! *)
42 :     {ty: X86MLTree.ty, src: X86Instr.operand} ->
43 :     {instrs : X86Instr.instruction list,(* the instructions *)
44 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
45 :     cleanup: X86Instr.instruction list (* cleanup code *)
46 :     }
47 : george 545 ) : sig include MLTREECOMP
48 :     val rewriteMemReg : bool
49 :     end =
50 : monnier 247 struct
51 :     structure T = X86MLTree
52 : monnier 429 structure S = T.Stream
53 : monnier 247 structure I = X86Instr
54 : george 545 structure C = I.C
55 :     structure Shuffle = Shuffle(I)
56 : monnier 247 structure W32 = Word32
57 : george 545 structure LE = I.LabelExp
58 :     structure A = MLRiscAnnotations
59 : monnier 247
60 : george 545 type instrStream = (I.instruction,C.regmap,C.cellset) T.stream
61 : george 555 type mltreeStream = (T.stm,C.regmap,T.mlrisc list) T.stream
62 : leunga 565
63 :     datatype kind = REAL | INTEGER
64 : george 545
65 :     structure Gen = MLTreeGen
66 :     (structure T = T
67 :     val intTy = 32
68 :     val naturalWidths = [32]
69 :     datatype rep = SE | ZE | NEITHER
70 :     val rep = NEITHER
71 :     )
72 :    
73 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
74 : monnier 247
75 : george 545 (* Should we perform automatic MemReg translation?
76 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
77 :     *)
78 :     val rewriteMemReg = rewriteMemReg
79 :     fun isMemReg r = rewriteMemReg andalso r >= 8 andalso r < 32
80 : monnier 247
81 : george 555 val ST0 = C.ST 0
82 :     val ST7 = C.ST 7
83 :    
84 : george 545 (*
85 :     * The code generator
86 :     *)
87 : monnier 411 fun selectInstructions
88 : george 545 (instrStream as
89 :     S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,
90 : monnier 429 beginCluster,endCluster,exitBlock,alias,phi,comment,...}) =
91 : george 545 let exception EA
92 : monnier 411
93 : george 545 (* label where a trap is generated -- one per cluster *)
94 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
95 : monnier 247
96 : george 545 (* effective address of an integer register *)
97 :     fun IntReg r = if isMemReg r then MemReg r else I.Direct r
98 :     and MemReg r =
99 :     ((* memRegsUsed := Word.orb(!memRegsUsed,
100 :     Word.<<(0w1, Word.fromInt r-0w8)); *)
101 :     I.MemReg r
102 :     )
103 : monnier 411
104 : george 545 (* Add an overflow trap *)
105 :     fun trap() =
106 :     let val jmp =
107 :     case !trapLabel of
108 :     NONE => let val label = Label.newLabel "trap"
109 :     val jmp = I.JCC{cond=I.O,
110 :     opnd=I.ImmedLabel(LE.LABEL label)}
111 :     in trapLabel := SOME(jmp, label); jmp end
112 :     | SOME(jmp, _) => jmp
113 :     in emit jmp end
114 : monnier 411
115 : george 545 val newReg = C.newReg
116 :     val newFreg = C.newFreg
117 : monnier 247
118 : george 545 (* mark an expression with a list of annotations *)
119 :     fun mark'(i,[]) = i
120 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
121 : monnier 247
122 : george 545 (* annotate an expression and emit it *)
123 :     fun mark(i,an) = emit(mark'(i,an))
124 : monnier 247
125 : george 545 (* emit parallel copies for integers
126 :     * Translates parallel copies that involve memregs into
127 :     * individual copies.
128 :     *)
129 :     fun copy([], [], an) = ()
130 :     | copy(dst, src, an) =
131 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
132 :     if rd = rs then [] else
133 :     let val tmpR = I.Direct(newReg())
134 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
135 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
136 :     end
137 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
138 :     if rd = rs then []
139 :     else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
140 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
141 :     in
142 :     app emit (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
143 :     {regmap=fn r => r, tmp=SOME(I.Direct(newReg())),
144 :     dst=dst, src=src})
145 :     end
146 :    
147 :     (* conversions *)
148 :     val itow = Word.fromInt
149 :     val wtoi = Word.toInt
150 :     fun toInt32 i = Int32.fromLarge(Int.toLarge i)
151 :     val w32toi32 = Word32.toLargeIntX
152 :     val i32tow32 = Word32.fromLargeInt
153 : monnier 247
154 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
155 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
156 : monnier 247
157 : george 545 (* some useful registers *)
158 :     val eax = I.Direct(C.eax)
159 :     val ecx = I.Direct(C.ecx)
160 :     val edx = I.Direct(C.edx)
161 : monnier 247
162 : george 545 fun immedLabel lab = I.ImmedLabel(LE.LABEL lab)
163 :    
164 :     (* Is the expression zero? *)
165 :     fun isZero(T.LI 0) = true
166 :     | isZero(T.LI32 0w0) = true
167 :     | isZero(T.MARK(e,a)) = isZero e
168 :     | isZero _ = false
169 :     (* Does the expression set the zero bit?
170 :     * WARNING: we assume these things are not optimized out!
171 :     *)
172 :     fun setZeroBit(T.ANDB _) = true
173 :     | setZeroBit(T.ORB _) = true
174 :     | setZeroBit(T.XORB _) = true
175 :     | setZeroBit(T.SRA _) = true
176 :     | setZeroBit(T.SRL _) = true
177 :     | setZeroBit(T.SLL _) = true
178 : leunga 695 | setZeroBit(T.SUB _) = true
179 :     | setZeroBit(T.ADDT _) = true
180 :     | setZeroBit(T.SUBT _) = true
181 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
182 :     | setZeroBit _ = false
183 : monnier 247
184 : leunga 695 fun setZeroBit2(T.ANDB _) = true
185 :     | setZeroBit2(T.ORB _) = true
186 :     | setZeroBit2(T.XORB _) = true
187 :     | setZeroBit2(T.SRA _) = true
188 :     | setZeroBit2(T.SRL _) = true
189 :     | setZeroBit2(T.SLL _) = true
190 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
191 :     | setZeroBit2(T.SUB _) = true
192 :     | setZeroBit2(T.ADDT _) = true
193 :     | setZeroBit2(T.SUBT _) = true
194 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
195 :     | setZeroBit2 _ = false
196 :    
197 : george 545 (* emit parallel copies for floating point *)
198 :     fun fcopy(fty, [], [], _) = ()
199 :     | fcopy(fty, dst as [_], src as [_], an) =
200 :     mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
201 :     | fcopy(fty, dst, src, an) =
202 :     mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
203 : monnier 247
204 : george 545 (* Translates MLTREE condition code to x86 condition code *)
205 :     fun cond T.LT = I.LT | cond T.LTU = I.B
206 :     | cond T.LE = I.LE | cond T.LEU = I.BE
207 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
208 :     | cond T.GE = I.GE | cond T.GEU = I.AE
209 :     | cond T.GT = I.GT | cond T.GTU = I.A
210 : monnier 247
211 : george 545 (* Move and annotate *)
212 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
213 :     if s=d then ()
214 :     else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
215 :     | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
216 : monnier 247
217 : george 545 (* Move only! *)
218 :     fun move(src, dst) = move'(src, dst, [])
219 : monnier 247
220 : george 545 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
221 : monnier 247
222 : george 545 val readonly = I.Region.readonly
223 : monnier 247
224 : george 545 (*
225 :     * Compute an effective address. This is a new version
226 :     *)
227 :     fun address(ea, mem) =
228 :     let (* tricky way to negate without overflow! *)
229 :     fun neg32 w = Word32.notb w + 0w1
230 : monnier 247
231 : george 545 (* Keep building a bigger and bigger effective address expressions
232 :     * The input is a list of trees
233 :     * b -- base
234 :     * i -- index
235 :     * s -- scale
236 :     * d -- immed displacement
237 :     *)
238 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
239 :     | doEA(t::trees, b, i, s, d) =
240 :     (case t of
241 :     T.LI n => doEAImmed(trees, n, b, i, s, d)
242 :     | T.LI32 n => doEAImmedw(trees, n, b, i, s, d)
243 :     | T.CONST c => doEALabel(trees, LE.CONST c, b, i, s, d)
244 :     | T.LABEL le => doEALabel(trees, le, b, i, s, d)
245 :     | T.ADD(32, t1, t2 as T.REG(_,r)) =>
246 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
247 :     else doEA(t1::t2::trees, b, i, s, d)
248 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
249 :     | T.SUB(32, t1, T.LI n) =>
250 :     (* can't overflow here *)
251 :     doEA(t1::T.LI32(neg32(Word32.fromInt n))::trees, b, i, s, d)
252 :     | T.SUB(32, t1, T.LI32 n) =>
253 :     doEA(t1::T.LI32(neg32 n)::trees, b, i, s, d)
254 :     | T.SLL(32, t1, T.LI 0) => displace(trees, t1, b, i, s, d)
255 :     | T.SLL(32, t1, T.LI 1) => indexed(trees, t1, t, 1, b, i, s, d)
256 :     | T.SLL(32, t1, T.LI 2) => indexed(trees, t1, t, 2, b, i, s, d)
257 :     | T.SLL(32, t1, T.LI 3) => indexed(trees, t1, t, 3, b, i, s, d)
258 :     | T.SLL(32, t1, T.LI32 0w0) => displace(trees, t1, b, i, s, d)
259 :     | T.SLL(32, t1, T.LI32 0w1) => indexed(trees,t1,t,1,b,i,s,d)
260 :     | T.SLL(32, t1, T.LI32 0w2) => indexed(trees,t1,t,2,b,i,s,d)
261 :     | T.SLL(32, t1, T.LI32 0w3) => indexed(trees,t1,t,3,b,i,s,d)
262 :     | t => displace(trees, t, b, i, s, d)
263 :     )
264 : monnier 247
265 : george 545 (* Add an immed constant *)
266 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
267 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
268 :     doEA(trees, b, i, s, (* no overflow! *)
269 :     I.Immed(w32toi32(Word32.fromInt n + i32tow32 m)))
270 :     | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
271 :     doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,LE.INT n)))
272 :     | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
273 : monnier 247
274 : george 545 (* Add an immed32 constant *)
275 :     and doEAImmedw(trees, 0w0, b, i, s, d) = doEA(trees, b, i, s, d)
276 :     | doEAImmedw(trees, n, b, i, s, I.Immed m) =
277 :     (* no overflow! *)
278 :     doEA(trees, b, i, s, I.Immed(w32toi32(i32tow32 m + n)))
279 :     | doEAImmedw(trees, n, b, i, s, I.ImmedLabel le) =
280 :     doEA(trees, b, i, s,
281 :     I.ImmedLabel(LE.PLUS(le,LE.INT(Word32.toIntX n)))
282 :     handle Overflow => error "doEAImmedw: constant too large")
283 :     | doEAImmedw(trees, n, b, i, s, _) = error "doEAImmedw"
284 : monnier 247
285 : george 545 (* Add a label expression *)
286 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
287 :     doEA(trees, b, i, s, I.ImmedLabel le)
288 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
289 :     doEA(trees, b, i, s,
290 :     I.ImmedLabel(LE.PLUS(le,LE.INT(Int32.toInt m)))
291 :     handle Overflow => error "doEALabel: constant too large")
292 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
293 :     doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,le')))
294 :     | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
295 : monnier 247
296 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
297 :     | makeAddressingMode(SOME base, NONE, _, disp) =
298 :     I.Displace{base=base, disp=disp, mem=mem}
299 :     | makeAddressingMode(base, SOME index, scale, disp) =
300 :     I.Indexed{base=base, index=index, scale=scale,
301 :     disp=disp, mem=mem}
302 : monnier 247
303 : george 545 (* generate code for tree and ensure that it is not in %esp *)
304 :     and exprNotEsp tree =
305 :     let val r = expr tree
306 :     in if r = C.esp then
307 :     let val tmp = newReg()
308 :     in move(I.Direct r, I.Direct tmp); tmp end
309 :     else r
310 :     end
311 : monnier 247
312 : george 545 (* Add a base register *)
313 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
314 :     doEA(trees, SOME(expr t), i, s, d)
315 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
316 :     (* make t the index, but make sure that it is not %esp! *)
317 :     let val i = expr t
318 :     in if i = C.esp then
319 :     (* swap base and index *)
320 :     if base <> C.esp then
321 :     doEA(trees, SOME i, b, 0, d)
322 :     else (* base and index = %esp! *)
323 :     let val index = newReg()
324 :     in move(I.Direct i, I.Direct index);
325 :     doEA(trees, b, SOME index, 0, d)
326 :     end
327 :     else
328 :     doEA(trees, b, SOME i, 0, d)
329 :     end
330 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
331 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
332 :     in doEA(trees, SOME b, i, s, d) end
333 : monnier 247
334 : george 545 (* Add an indexed register *)
335 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
336 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
337 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
338 :     doEA(trees, SOME(expr t0), i, s, d)
339 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
340 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
341 :     in doEA(trees, SOME b, i, s, d) end
342 :    
343 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
344 :     I.Immed _ => raise EA
345 :     | I.ImmedLabel le => I.LabelEA le
346 :     | ea => ea
347 :     end (* address *)
348 : monnier 247
349 : george 545 (* reduce an expression into an operand *)
350 :     and operand(T.LI i) = I.Immed(toInt32 i)
351 :     | operand(T.LI32 w) = I.Immed(wToInt32 w)
352 :     | operand(T.CONST c) = I.ImmedLabel(LE.CONST c)
353 :     | operand(T.LABEL lab) = I.ImmedLabel lab
354 :     | operand(T.REG(_,r)) = IntReg r
355 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
356 :     | operand(t) = I.Direct(expr t)
357 : monnier 247
358 : george 545 and moveToReg(opnd) =
359 :     let val dst = I.Direct(newReg())
360 :     in move(opnd, dst); dst
361 :     end
362 : monnier 247
363 : george 545 and reduceOpnd(I.Direct r) = r
364 :     | reduceOpnd opnd =
365 :     let val dst = newReg()
366 :     in move(opnd, I.Direct dst); dst
367 :     end
368 : monnier 247
369 : george 545 (* ensure that the operand is either an immed or register *)
370 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
371 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
372 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
373 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
374 :     | immedOrReg opnd = opnd
375 : monnier 247
376 : george 545 and isImmediate(I.Immed _) = true
377 :     | isImmediate(I.ImmedLabel _) = true
378 :     | isImmediate _ = false
379 : monnier 247
380 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
381 :    
382 :     and isMemOpnd opnd =
383 :     (case opnd of
384 :     I.Displace _ => true
385 :     | I.Indexed _ => true
386 :     | I.MemReg _ => true
387 :     | I.LabelEA _ => true
388 : george 555 | I.FDirect f => true
389 : george 545 | _ => false
390 :     )
391 :    
392 :     (*
393 :     * Compute an integer expression and put the result in
394 :     * the destination register rd.
395 :     *)
396 :     and doExpr(exp, rd : I.C.cell, an) =
397 :     let val rdOpnd = IntReg rd
398 : monnier 247
399 : george 545 fun equalRd(I.Direct r) = r = rd
400 :     | equalRd(I.MemReg r) = r = rd
401 :     | equalRd _ = false
402 : monnier 247
403 : george 545 (* Emit a binary operator. If the destination is
404 :     * a memReg, do something smarter.
405 :     *)
406 :     fun genBinary(binOp, opnd1, opnd2) =
407 :     if isMemReg rd andalso
408 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
409 :     equalRd(opnd2)
410 :     then
411 :     let val tmpR = newReg()
412 :     val tmp = I.Direct tmpR
413 :     in move(opnd1, tmp);
414 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
415 :     move(tmp, rdOpnd)
416 :     end
417 :     else
418 :     (move(opnd1, rdOpnd);
419 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
420 :     )
421 : monnier 247
422 : george 545 (* Generate a binary operator; it may commute *)
423 :     fun binaryComm(binOp, e1, e2) =
424 :     let val (opnd1, opnd2) =
425 :     case (operand e1, operand e2) of
426 :     (x as I.Immed _, y) => (y, x)
427 :     | (x as I.ImmedLabel _, y) => (y, x)
428 :     | (x, y as I.Direct _) => (y, x)
429 :     | (x, y) => (x, y)
430 :     in genBinary(binOp, opnd1, opnd2)
431 :     end
432 :    
433 :     (* Generate a binary operator; non-commutative *)
434 :     fun binary(binOp, e1, e2) =
435 :     genBinary(binOp, operand e1, operand e2)
436 :    
437 :     (* Generate a unary operator *)
438 :     fun unary(unOp, e) =
439 :     let val opnd = operand e
440 :     in if isMemReg rd andalso isMemOpnd opnd then
441 :     let val tmp = I.Direct(newReg())
442 :     in move(opnd, tmp); move(tmp, rdOpnd)
443 :     end
444 :     else move(opnd, rdOpnd);
445 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
446 :     end
447 :    
448 :     (* Generate shifts; the shift
449 :     * amount must be a constant or in %ecx *)
450 :     fun shift(opcode, e1, e2) =
451 :     let val (opnd1, opnd2) = (operand e1, operand e2)
452 :     in case opnd2 of
453 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
454 :     | _ =>
455 :     if equalRd(opnd2) then
456 :     let val tmpR = newReg()
457 :     val tmp = I.Direct tmpR
458 :     in move(opnd1, tmp);
459 :     move(opnd2, ecx);
460 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
461 :     move(tmp, rdOpnd)
462 :     end
463 :     else
464 :     (move(opnd1, rdOpnd);
465 :     move(opnd2, ecx);
466 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
467 :     )
468 :     end
469 :    
470 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
471 :     fun divrem(signed, overflow, e1, e2, resultReg) =
472 :     let val (opnd1, opnd2) = (operand e1, operand e2)
473 :     val _ = move(opnd1, eax)
474 : leunga 606 val oper = if signed then (emit(I.CDQ); I.IDIVL)
475 :     else (zero edx; I.DIVL)
476 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
477 :     move(resultReg, rdOpnd);
478 :     if overflow then trap() else ()
479 :     end
480 :    
481 :     (* Optimize the special case for division *)
482 :     fun divide(signed, overflow, e1, e2 as T.LI n) =
483 :     let fun isPowerOf2 w = Word.andb((w - 0w1), w) = 0w0
484 :     fun log2 n = (* n must be > 0!!! *)
485 :     let fun loop(0w1,pow) = pow
486 :     | loop(w,pow) = loop(Word.>>(w, 0w1),pow+1)
487 :     in loop(n,0) end
488 :     val w = Word.fromInt n
489 :     in if n > 1 andalso isPowerOf2 w then
490 :     let val pow = T.LI(log2 w)
491 :     in if signed then
492 :     (* signed; simulate round towards zero *)
493 :     let val label = Label.newLabel ""
494 :     val reg1 = expr e1
495 :     val opnd1 = I.Direct reg1
496 :     in if setZeroBit e1 then ()
497 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
498 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
499 :     emit(if n = 2 then
500 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
501 :     else
502 :     I.BINARY{binOp=I.ADDL,
503 :     src=I.Immed(toInt32 n - 1),
504 :     dst=opnd1});
505 :     defineLabel label;
506 :     shift(I.SARL, T.REG(32, reg1), pow)
507 :     end
508 :     else (* unsigned *)
509 :     shift(I.SHRL, e1, pow)
510 :     end
511 :     else
512 :     (* note the only way we can overflow is if
513 :     * n = 0 or n = -1
514 :     *)
515 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
516 :     e1, e2, eax)
517 :     end
518 :     | divide(signed, overflow, e1, e2) =
519 :     divrem(signed, overflow, e1, e2, eax)
520 : monnier 247
521 : george 545 fun rem(signed, overflow, e1, e2) =
522 :     divrem(signed, overflow, e1, e2, edx)
523 :    
524 :     (* unsigned integer multiplication *)
525 :     fun uMultiply(e1, e2) =
526 :     (* note e2 can never be (I.Direct edx) *)
527 :     (move(operand e1, eax);
528 : leunga 606 mark(I.MULTDIV{multDivOp=I.MULL,
529 : george 545 src=regOrMem(operand e2)},an);
530 :     move(eax, rdOpnd)
531 :     )
532 :    
533 :     (* signed integer multiplication:
534 :     * The only forms that are allowed that also sets the
535 :     * OF and CF flags are:
536 :     *
537 :     * imul r32, r32/m32, imm8
538 :     * imul r32, imm8
539 :     * imul r32, imm32
540 :     *)
541 :     fun multiply(e1, e2) =
542 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _, dstR, dst) =
543 :     (move(i1, dst);
544 :     mark(I.MUL3{dst=dstR, src1=i2, src2=NONE},an))
545 :     | doit(rm, i2 as I.Immed _, dstR, dst) =
546 :     doit(i2, rm, dstR, dst)
547 :     | doit(imm as I.Immed(i), rm, dstR, dst) =
548 :     mark(I.MUL3{dst=dstR, src1=rm, src2=SOME i},an)
549 :     | doit(r1 as I.Direct _, r2 as I.Direct _, dstR, dst) =
550 :     (move(r1, dst);
551 :     mark(I.MUL3{dst=dstR, src1=r2, src2=NONE},an))
552 :     | doit(r1 as I.Direct _, rm, dstR, dst) =
553 :     (move(r1, dst);
554 :     mark(I.MUL3{dst=dstR, src1=rm, src2=NONE},an))
555 :     | doit(rm, r as I.Direct _, dstR, dst) =
556 :     doit(r, rm, dstR, dst)
557 :     | doit(rm1, rm2, dstR, dst) =
558 :     if equalRd rm2 then
559 :     let val tmpR = newReg()
560 :     val tmp = I.Direct tmpR
561 :     in move(rm1, tmp);
562 :     mark(I.MUL3{dst=tmpR, src1=rm2, src2=NONE},an);
563 :     move(tmp, dst)
564 :     end
565 :     else
566 :     (move(rm1, dst);
567 :     mark(I.MUL3{dst=dstR, src1=rm2, src2=NONE},an)
568 :     )
569 :     val (opnd1, opnd2) = (operand e1, operand e2)
570 :     in if isMemReg rd then (* destination must be a real reg *)
571 :     let val tmpR = newReg()
572 :     val tmp = I.Direct tmpR
573 :     in doit(opnd1, opnd2, tmpR, tmp);
574 :     move(tmp, rdOpnd)
575 :     end
576 :     else
577 :     doit(opnd1, opnd2, rd, rdOpnd)
578 :     end
579 : monnier 247
580 : george 545 (* Makes sure the destination must be a register *)
581 :     fun dstMustBeReg f =
582 :     if isMemReg rd then
583 :     let val tmpR = newReg()
584 :     val tmp = I.Direct(tmpR)
585 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
586 :     else f(rd, rdOpnd)
587 : monnier 247
588 : george 545 (* Emit a load instruction; makes sure that the destination
589 :     * is a register
590 :     *)
591 :     fun genLoad(mvOp, ea, mem) =
592 :     dstMustBeReg(fn (_, dst) =>
593 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
594 :    
595 :     (* Generate a zero extended loads *)
596 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
597 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
598 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
599 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
600 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
601 :    
602 :     (* Generate a sign extended loads *)
603 :    
604 :     (* Generate setcc instruction:
605 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
606 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
607 :     * Note that we have to use eax as the destination of the
608 :     * setcc because it only works on the registers
609 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
610 :     * are inaccessible in 32 bit mode.
611 : george 545 *)
612 :     fun setcc(ty, cc, t1, t2, yes, no) =
613 : leunga 583 let val (cc, yes, no) =
614 :     if yes > no then (cc, yes, no)
615 :     else (T.Basis.negateCond cc, no, yes)
616 : george 545 in (* Clear the destination first.
617 :     * This this because stupid SETcc
618 :     * only writes to the low order
619 :     * byte. That's Intel architecture, folks.
620 :     *)
621 : leunga 695 case (yes, no, cc) of
622 :     (1, 0, T.LT) =>
623 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
624 :     in move(tmp, rdOpnd);
625 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
626 :     end
627 :     | (1, 0, T.GT) =>
628 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
629 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
630 :     move(tmp, rdOpnd);
631 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
632 :     end
633 :     | (1, 0, _) => (* normal case *)
634 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
635 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
636 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
637 : leunga 583 move(eax, rdOpnd)
638 :     end
639 : leunga 695 | (C1, C2, _) =>
640 : george 545 (* general case;
641 : leunga 583 * from the Intel optimization guide p3-5
642 :     *)
643 : leunga 695 let val _ = zero eax;
644 :     val cc = cmp(true, ty, cc, t1, t2, [])
645 : leunga 583 in case C1-C2 of
646 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
647 :     let val (base,scale) =
648 :     case D of
649 :     1 => (NONE, 0)
650 :     | 2 => (NONE, 1)
651 :     | 3 => (SOME C.eax, 1)
652 :     | 4 => (NONE, 2)
653 :     | 5 => (SOME C.eax, 2)
654 :     | 8 => (NONE, 3)
655 :     | 9 => (SOME C.eax, 3)
656 :     val addr = I.Indexed{base=base,
657 :     index=C.eax,
658 :     scale=scale,
659 :     disp=I.Immed C2,
660 : george 545 mem=readonly}
661 : leunga 583 val tmpR = newReg()
662 :     val tmp = I.Direct tmpR
663 :     in emit(I.SET{cond=cond cc, opnd=eax});
664 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
665 :     move(tmp, rdOpnd)
666 :     end
667 :     | D =>
668 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
669 :     opnd=eax});
670 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
671 :     emit(I.BINARY{binOp=I.ANDL,
672 :     src=I.Immed D, dst=eax});
673 :     if C2 = 0 then
674 :     move(eax, rdOpnd)
675 :     else
676 :     let val tmpR = newReg()
677 :     val tmp = I.Direct tmpR
678 :     in mark(I.LEA{addr=
679 :     I.Displace{
680 :     base=C.eax,
681 :     disp=I.Immed C2,
682 :     mem=readonly},
683 :     r32=tmpR}, an);
684 :     move(tmp, rdOpnd)
685 :     end
686 :     )
687 :     end
688 : george 545 end (* setcc *)
689 :    
690 :     (* Generate cmovcc instruction.
691 :     * on Pentium Pro and Pentium II only
692 :     *)
693 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
694 :     let fun genCmov(dstR, _) =
695 :     let val _ = doExpr(no, dstR, []) (* false branch *)
696 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
697 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
698 :     end
699 :     in dstMustBeReg genCmov
700 :     end
701 :    
702 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
703 : monnier 247
704 : leunga 606 (* Add n to rd *)
705 :     fun addN n =
706 :     let val n = operand n
707 :     val src = if isMemReg rd then immedOrReg n else n
708 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
709 :    
710 : george 545 (* Generate addition *)
711 :     fun addition(e1, e2) =
712 : leunga 606 case e1 of
713 :     T.REG(_,rs) => if rs = rd then addN e2 else addition1(e1,e2)
714 :     | _ => addition1(e1,e2)
715 :     and addition1(e1, e2) =
716 :     case e2 of
717 :     T.REG(_,rs) => if rs = rd then addN e1 else addition2(e1,e2)
718 :     | _ => addition2(e1,e2)
719 :     and addition2(e1,e2) =
720 : george 545 (dstMustBeReg(fn (dstR, _) =>
721 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
722 :     handle EA => binaryComm(I.ADDL, e1, e2))
723 : monnier 247
724 :    
725 : george 545 in case exp of
726 :     T.REG(_,rs) =>
727 :     if isMemReg rs andalso isMemReg rd then
728 :     let val tmp = I.Direct(newReg())
729 :     in move'(MemReg rs, tmp, an);
730 :     move'(tmp, rdOpnd, [])
731 :     end
732 :     else move'(IntReg rs, rdOpnd, an)
733 :     | (T.LI 0 | T.LI32 0w0) =>
734 :     (* As per Fermin's request, special optimization for rd := 0.
735 :     * Currently we don't bother with the size.
736 :     *)
737 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
738 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
739 :     | T.LI n => move'(I.Immed(toInt32 n), rdOpnd, an)
740 :     | T.LI32 w => move'(I.Immed(wToInt32 w), rdOpnd, an)
741 :     | T.CONST c => move'(I.ImmedLabel(LE.CONST c), rdOpnd, an)
742 :     | T.LABEL lab => move'(I.ImmedLabel lab, rdOpnd, an)
743 : monnier 247
744 : george 545 (* 32-bit addition *)
745 :     | T.ADD(32, e, (T.LI 1|T.LI32 0w1)) => unary(I.INCL, e)
746 :     | T.ADD(32, (T.LI 1|T.LI32 0w1), e) => unary(I.INCL, e)
747 :     | T.ADD(32, e, T.LI ~1) => unary(I.DECL, e)
748 :     | T.ADD(32, T.LI ~1, e) => unary(I.DECL, e)
749 :     | T.ADD(32, e1, e2) => addition(e1, e2)
750 : monnier 247
751 : leunga 695 (* 32-bit addition but set the flag!
752 :     * This is a stupid hack for now.
753 :     *)
754 :     | T.ADD(0, e, (T.LI 1|T.LI32 0w1)) => unary(I.INCL, e)
755 :     | T.ADD(0, (T.LI 1|T.LI32 0w1), e) => unary(I.INCL, e)
756 :     | T.ADD(0, e, T.LI ~1) => unary(I.DECL, e)
757 :     | T.ADD(0, T.LI ~1, e) => unary(I.DECL, e)
758 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
759 :    
760 : george 545 (* 32-bit subtraction *)
761 : leunga 695 | T.SUB(32, e, (T.LI 0 | T.LI32 0w0)) => doExpr(e, rd, an)
762 : george 545 | T.SUB(32, e, (T.LI 1 | T.LI32 0w1)) => unary(I.DECL, e)
763 :     | T.SUB(32, e, T.LI ~1) => unary(I.INCL, e)
764 :     | T.SUB(32, (T.LI 0 | T.LI32 0w0), e) => unary(I.NEGL, e)
765 : monnier 247
766 : george 545 (* Never mind:
767 :     | T.SUB(32, e1, e2 as T.LI n) =>
768 :     (mark(I.LEA{r32=rd, addr=address(T.ADD(32, e1, T.LI(~n)),
769 :     I.Region.readonly)}, an)
770 :     handle (Overflow|EA) => binary(I.SUBL, e1, e2))
771 :     *)
772 :     | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
773 : monnier 247
774 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
775 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
776 :     | T.REMU(32, x, y) => rem(false, false, x, y)
777 : monnier 247
778 : george 545 | T.MULS(32, x, y) => multiply(x, y)
779 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
780 :     | T.REMS(32, x, y) => rem(true, false, x, y)
781 : monnier 247
782 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
783 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
784 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
785 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
786 :     | T.REMT(32, x, y) => rem(true, true, x, y)
787 : monnier 247
788 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
789 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
790 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
791 :     | T.NOTB(32, x) => unary(I.NOTL, x)
792 : monnier 247
793 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
794 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
795 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
796 : monnier 247
797 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
798 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
799 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
800 :     | T.CVTI2I(_,T.SIGN_EXTEND,_,T.LOAD(8,ea,mem)) => load8s(ea, mem)
801 :     | T.CVTI2I(_,T.SIGN_EXTEND,_,T.LOAD(16,ea,mem)) => load16s(ea, mem)
802 : monnier 498
803 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
804 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
805 :     | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI32 yes, T.LI32 no) =>
806 :     setcc(ty, cc, t1, t2, Word32.toLargeIntX yes,
807 :     Word32.toLargeIntX no)
808 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
809 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
810 :     Pentium => unknownExp exp
811 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
812 :     )
813 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
814 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
815 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
816 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
817 : george 555 | T.REXT e =>
818 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
819 : george 545 (* simplify and try again *)
820 :     | exp => unknownExp exp
821 :     end (* doExpr *)
822 : monnier 247
823 : george 545 (* generate an expression and return its result register
824 :     * If rewritePseudo is on, the result is guaranteed to be in a
825 :     * non memReg register
826 :     *)
827 :     and expr(exp as T.REG(_, rd)) =
828 :     if isMemReg rd then genExpr exp else rd
829 :     | expr exp = genExpr exp
830 : monnier 247
831 : george 545 and genExpr exp =
832 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
833 : monnier 247
834 : george 545 (* Compare an expression with zero.
835 :     * On the x86, TEST is superior to AND for doing the same thing,
836 :     * since it doesn't need to write out the result in a register.
837 :     *)
838 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
839 : george 545 (case ty of
840 : leunga 695 8 => test(I.TESTB, a, b, an)
841 :     | 16 => test(I.TESTW, a, b, an)
842 :     | 32 => test(I.TESTL, a, b, an)
843 :     | _ => doExpr(e, newReg(), an);
844 :     cc)
845 :     | cmpWithZero(cc, e, an) =
846 :     let val e =
847 :     case e of (* hack to disable the lea optimization XXX *)
848 :     T.ADD(_, a, b) => T.ADD(0, a, b)
849 :     | e => e
850 :     in doExpr(e, newReg(), an); cc end
851 : monnier 247
852 : george 545 (* Emit a test.
853 :     * The available modes are
854 :     * r/m, r
855 :     * r/m, imm
856 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
857 :     * When anding an operand with a constant
858 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
859 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
860 :     * this works for memory operands too. However, with TESTB, it is
861 :     * not possible to use registers other than
862 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
863 :     * perform register allocation first, and if the operand registers
864 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
865 :     * by TESTB.
866 :     *)
867 : leunga 695 and test(testopcode, a, b, an) =
868 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
869 :     (* translate r, r/m => r/m, r *)
870 :     val (opnd1, opnd2) =
871 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
872 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
873 : george 545 end
874 : monnier 247
875 : george 545 (* generate a condition code expression
876 :     * The zero is for setting the condition code!
877 :     * I have no idea why this is used.
878 :     *)
879 :     and doCCexpr(T.CMP(ty, cc, t1, t2), 0, an) =
880 :     (cmp(false, ty, cc, t1, t2, an); ())
881 :     | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
882 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
883 :     | doCCexpr(T.CCEXT e, cd, an) =
884 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
885 : george 545 | doCCexpr _ = error "doCCexpr"
886 : monnier 247
887 : george 545 and ccExpr e = error "ccExpr"
888 : monnier 247
889 : george 545 (* generate a comparison and sets the condition code;
890 :     * return the actual cc used. If the flag swapable is true,
891 :     * we can also reorder the operands.
892 :     *)
893 :     and cmp(swapable, ty, cc, t1, t2, an) =
894 : leunga 695 (* == and <> can be always be reordered *)
895 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
896 :     in (* Sometimes the comparison is not necessary because
897 :     * the bits are already set!
898 :     *)
899 :     if isZero t1 andalso setZeroBit2 t2 then
900 :     if swapable then
901 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
902 :     else (* can't reorder the comparison! *)
903 :     genCmp(ty, false, cc, t1, t2, an)
904 :     else if isZero t2 andalso setZeroBit2 t1 then
905 :     cmpWithZero(cc, t1, an)
906 :     else genCmp(ty, swapable, cc, t1, t2, an)
907 :     end
908 : monnier 247
909 : george 545 (* Give a and b which are the operands to a comparison (or test)
910 :     * Return the appropriate condition code and operands.
911 :     * The available modes are:
912 :     * r/m, imm
913 :     * r/m, r
914 :     * r, r/m
915 :     *)
916 :     and commuteComparison(cc, swapable, a, b) =
917 :     let val (opnd1, opnd2) = (operand a, operand b)
918 :     in (* Try to fold in the operands whenever possible *)
919 :     case (isImmediate opnd1, isImmediate opnd2) of
920 :     (true, true) => (cc, moveToReg opnd1, opnd2)
921 :     | (true, false) =>
922 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
923 :     else (cc, moveToReg opnd1, opnd2)
924 :     | (false, true) => (cc, opnd1, opnd2)
925 :     | (false, false) =>
926 :     (case (opnd1, opnd2) of
927 :     (_, I.Direct _) => (cc, opnd1, opnd2)
928 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
929 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
930 :     )
931 :     end
932 :    
933 :     (* generate a real comparison; return the real cc used *)
934 :     and genCmp(ty, swapable, cc, a, b, an) =
935 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
936 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
937 :     end
938 : monnier 247
939 : george 545 (* generate code for jumps *)
940 :     and jmp(T.LABEL(lexp as LE.LABEL lab), labs, an) =
941 :     mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
942 :     | jmp(T.LABEL lexp, labs, an) = mark(I.JMP(I.ImmedLabel lexp, labs), an)
943 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
944 :    
945 :     (* convert mlrisc to cellset:
946 :     *)
947 :     and cellset mlrisc =
948 :     let val addCCReg = C.addCell C.CC
949 :     fun g([],acc) = acc
950 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
951 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
952 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
953 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
954 :     | g(_::regs, acc) = g(regs, acc)
955 :     in g(mlrisc, C.empty) end
956 :    
957 :     (* generate code for calls *)
958 :     and call(ea, flow, def, use, mem, an) =
959 :     mark(I.CALL(operand ea,cellset(def),cellset(use),mem),an)
960 :    
961 :     (* generate code for integer stores *)
962 :     and store8(ea, d, mem, an) =
963 :     let val src = (* movb has to use %eax as source. Stupid x86! *)
964 :     case immedOrReg(operand d) of
965 :     src as I.Direct r =>
966 :     if r = C.eax then src else (move(src, eax); eax)
967 :     | src => src
968 :     in mark(I.MOVE{mvOp=I.MOVB, src=src, dst=address(ea,mem)},an)
969 :     end
970 :     and store16(ea, d, mem, an) = error "store16"
971 :     and store32(ea, d, mem, an) =
972 :     move'(immedOrReg(operand d), address(ea, mem), an)
973 :    
974 :     (* generate code for branching *)
975 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
976 :     (* allow reordering of operands *)
977 :     let val cc = cmp(true, ty, cc, t1, t2, [])
978 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
979 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
980 :     fbranch(fty, fcc, t1, t2, lab, an)
981 :     | branch(ccexp, lab, an) =
982 :     (doCCexpr(ccexp, 0, []);
983 :     mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
984 :     )
985 :    
986 :     (* generate code for floating point compare and branch *)
987 :     and fbranch(fty, fcc, t1, t2, lab, an) =
988 :     let fun compare() =
989 :     let fun ignoreOrder (T.FREG _) = true
990 :     | ignoreOrder (T.FLOAD _) = true
991 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
992 :     | ignoreOrder _ = false
993 :     in if ignoreOrder t1 orelse ignoreOrder t2 then
994 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
995 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
996 :     emit(I.FXCH{opnd=C.ST(1)}));
997 :     emit(I.FUCOMPP)
998 : monnier 411 end
999 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1000 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1001 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1002 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1003 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1004 :     fun sahf() = emit(I.SAHF)
1005 :     fun branch() =
1006 :     case fcc
1007 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1008 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1009 :     | T.? => (sahf(); j(I.P,lab))
1010 :     | T.<=> => (sahf(); j(I.NP,lab))
1011 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1012 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1013 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1014 :     | T.?< => (testil 0x500; j(I.NE,lab))
1015 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1016 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1017 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1018 :     cmpil 0x4000; j(I.EQ,lab))
1019 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1020 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1021 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1022 : george 545 | _ => error "fbranch"
1023 :     (*esac*)
1024 :     in compare(); emit I.FNSTSW; branch()
1025 : monnier 411 end
1026 : monnier 247
1027 : george 545 and fld(32, opnd) = I.FLDS opnd
1028 :     | fld(64, opnd) = I.FLDL opnd
1029 : george 555 | fld(80, opnd) = I.FLDT opnd
1030 : george 545 | fld _ = error "fld"
1031 :    
1032 : leunga 565 and fild(16, opnd) = I.FILD opnd
1033 :     | fild(32, opnd) = I.FILDL opnd
1034 :     | fild(64, opnd) = I.FILDLL opnd
1035 :     | fild _ = error "fild"
1036 :    
1037 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1038 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1039 :    
1040 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1041 :     | fstp(64, opnd) = I.FSTPL opnd
1042 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1043 : george 545 | fstp _ = error "fstp"
1044 :    
1045 :     (* generate code for floating point stores *)
1046 :     and fstore(fty, ea, d, mem, an) =
1047 :     (case d of
1048 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1049 :     | _ => reduceFexp(fty, d, []);
1050 :     mark(fstp(fty, address(ea, mem)), an)
1051 :     )
1052 :    
1053 : leunga 593 and fexpr e = (reduceFexp(64, e, []); C.ST(0))
1054 : george 545
1055 :     (* generate floating point expression and put the result in fd *)
1056 :     and doFexpr(fty, T.FREG(_, fs), fd, an) =
1057 :     (if fs = fd then ()
1058 :     else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
1059 :     )
1060 :     | doFexpr(fty, T.FLOAD(fty', ea, mem), fd, an) =
1061 :     let val ea = address(ea, mem)
1062 :     in mark(fld(fty', ea), an);
1063 : leunga 624 if fd = ST0 then () else emit(fstp(fty, I.FDirect fd))
1064 : george 545 end
1065 :     | doFexpr(fty, e, fd, an) =
1066 :     (reduceFexp(fty, e, []);
1067 : leunga 624 if fd = ST0 then () else mark(fstp(fty, I.FDirect fd), an)
1068 : george 545 )
1069 :    
1070 :     (*
1071 :     * Generate floating point expression using Sethi-Ullman's scheme:
1072 :     * This function evaluates a floating point expression,
1073 :     * and put result in %ST(0).
1074 :     *)
1075 :     and reduceFexp(fty, fexp, an) =
1076 : george 555 let val ST = I.ST(C.ST 0)
1077 :     val ST1 = I.ST(C.ST 1)
1078 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1079 : george 545
1080 : leunga 565 datatype su_tree =
1081 :     LEAF of int * T.fexp * ans
1082 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1083 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1084 :     and fbinop = FADD | FSUB | FMUL | FDIV
1085 :     | FIADD | FISUB | FIMUL | FIDIV
1086 :     withtype ans = Annotations.annotations
1087 : monnier 247
1088 : leunga 565 fun label(LEAF(n, _, _)) = n
1089 :     | label(BINARY(n, _, _, _, _, _)) = n
1090 :     | label(UNARY(n, _, _, _, _)) = n
1091 : george 545
1092 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1093 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1094 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1095 : george 545
1096 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1097 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1098 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1099 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1100 :     | su(T.CVTF2F(_, _, t)) = su t
1101 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1102 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1103 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1104 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1105 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1106 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1107 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1108 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1109 :     | su _ = error "su"
1110 :    
1111 :     (* Try to fold the the memory operand or integer conversion *)
1112 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1113 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1114 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1115 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1116 :     | suFold(T.FMARK(t, a)) =
1117 :     let val (t, integer) = suFold t
1118 :     in (annotate(t, a), integer) end
1119 :     | suFold e = (su e, false)
1120 :    
1121 :     (* Can the tree be folded into the src operand? *)
1122 :     and foldable(T.FREG _) = true
1123 :     | foldable(T.FLOAD _) = true
1124 :     | foldable(T.CVTI2F(_, (16 | 32), _)) = true
1125 :     | foldable(T.CVTF2F(_, _, t)) = foldable t
1126 :     | foldable(T.FMARK(t, _)) = foldable t
1127 :     | foldable _ = false
1128 :    
1129 :     (* Form unary tree *)
1130 :     and suUnary(fty, funary, t) =
1131 :     let val t = su t
1132 :     in UNARY(label t, fty, funary, t, [])
1133 : george 545 end
1134 : leunga 565
1135 :     (* Form binary tree *)
1136 :     and suBinary(fty, binop, ibinop, t1, t2) =
1137 :     let val t1 = su t1
1138 :     val (t2, integer) = suFold t2
1139 :     val n1 = label t1
1140 :     val n2 = label t2
1141 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1142 :     val myOp = if integer then ibinop else binop
1143 :     in BINARY(n, fty, myOp, t1, t2, [])
1144 : george 545 end
1145 : george 555
1146 : leunga 565 (* Try to fold in the operand if possible.
1147 :     * This only applies to commutative operations.
1148 :     *)
1149 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1150 :     let val (t1, t2) = if foldable t2 then (t1, t2) else (t2, t1)
1151 :     in suBinary(fty, binop, ibinop, t1, t2) end
1152 :    
1153 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1154 :     LEAF(_, T.FREG(t2,f2), [])) = t1=t2 andalso f1=f2
1155 :     | sameTree _ = false
1156 :    
1157 :     (* Traverse tree and generate code *)
1158 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1159 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1160 :     let val _ = gencode x
1161 :     val (_, fty, src) = leafEA y
1162 :     fun gen(code) = mark(code, a1 @ a2)
1163 :     fun binary(oper32, oper64) =
1164 :     if sameTree(x, t2) then
1165 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1166 : george 555 else
1167 :     let val oper =
1168 : leunga 565 if isMemOpnd src then
1169 :     case fty of
1170 :     32 => oper32
1171 :     | 64 => oper64
1172 :     | _ => error "gencode: BINARY"
1173 :     else oper64
1174 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1175 :     fun ibinary(oper16, oper32) =
1176 :     let val oper = case fty of
1177 :     16 => oper16
1178 :     | 32 => oper32
1179 :     | _ => error "gencode: IBINARY"
1180 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1181 :     in case binop of
1182 :     FADD => binary(I.FADDS, I.FADDL)
1183 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1184 :     | FMUL => binary(I.FMULS, I.FMULL)
1185 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1186 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1187 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1188 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1189 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1190 :     end
1191 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1192 :     let fun doit(t1, t2, oper, operP, operRP) =
1193 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1194 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1195 :     *)
1196 :     val n1 = label t1
1197 :     val n2 = label t2
1198 :     in if n1 < n2 andalso n1 <= 7 then
1199 :     (gencode t2;
1200 :     gencode t1;
1201 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1202 :     else if n2 <= n1 andalso n2 <= 7 then
1203 :     (gencode t1;
1204 :     gencode t2;
1205 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1206 :     else
1207 :     let (* both labels > 7 *)
1208 :     val fs = I.FDirect(newFreg())
1209 :     in gencode t2;
1210 :     emit(fstp(fty, fs));
1211 :     gencode t1;
1212 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1213 :     end
1214 :     end
1215 :     in case binop of
1216 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1217 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1218 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1219 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1220 : george 545 | _ => error "gencode.BINARY"
1221 :     end
1222 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1223 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1224 :    
1225 :     (* Generate code for a leaf.
1226 :     * Returns the type and an effective address
1227 :     *)
1228 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1229 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1230 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1231 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1232 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1233 : leunga 565 | leafEA _ = error "leafEA"
1234 :    
1235 :     (* Move integer t of size ty into a memory location *)
1236 : leunga 593 and int2real(ty, t) =
1237 : leunga 565 let val opnd = operand t
1238 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1239 :     then (INTEGER, ty, opnd)
1240 : leunga 593 else
1241 :     let val {instrs, tempMem, cleanup} =
1242 :     cvti2f{ty=ty, src=opnd}
1243 :     in app emit instrs;
1244 :     cleanupCode := !cleanupCode @ cleanup;
1245 :     (INTEGER, 32, tempMem)
1246 :     end
1247 : george 545 end
1248 : leunga 593 in gencode(su fexp);
1249 :     app emit(!cleanupCode)
1250 : george 545 end (*reduceFexp*)
1251 :    
1252 :     (* generate code for a statement *)
1253 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1254 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1255 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1256 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1257 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1258 :     | stmt(T.JMP(ctrl, e, labs), an) = jmp(e, labs, an)
1259 : leunga 591 | stmt(T.CALL{funct, targets, defs, uses, cdefs, cuses, region}, an) =
1260 :     call(funct,targets,defs,uses,region,an)
1261 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1262 :     | stmt(T.STORE(8, ea, d, mem), an) = store8(ea, d, mem, an)
1263 :     | stmt(T.STORE(16, ea, d, mem), an) = store16(ea, d, mem, an)
1264 :     | stmt(T.STORE(32, ea, d, mem), an) = store32(ea, d, mem, an)
1265 :     | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1266 :     | stmt(T.BCC(ctrl, cc, lab), an) = branch(cc, lab, an)
1267 :     | stmt(T.DEFINE l, _) = defineLabel l
1268 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1269 : george 555 | stmt(T.EXT s, an) =
1270 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1271 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1272 :    
1273 :     and doStmt s = stmt(s, [])
1274 :     and doStmts ss = app doStmt ss
1275 :    
1276 :     and beginCluster' _ =
1277 :     ((* Must be cleared by the client.
1278 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1279 :     *)
1280 :     trapLabel := NONE; beginCluster 0)
1281 :     and endCluster' a =
1282 : monnier 247 (case !trapLabel
1283 : monnier 411 of NONE => ()
1284 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1285 : monnier 411 (*esac*);
1286 : george 545 endCluster(a)
1287 :     )
1288 :    
1289 :     and reducer() =
1290 :     T.REDUCER{reduceRexp = expr,
1291 :     reduceFexp = fexpr,
1292 :     reduceCCexp = ccExpr,
1293 :     reduceStm = stmt,
1294 :     operand = operand,
1295 :     reduceOperand = reduceOpnd,
1296 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1297 :     emit = mark,
1298 :     instrStream = instrStream,
1299 :     mltreeStream = self()
1300 :     }
1301 :    
1302 :     and self() =
1303 :     S.STREAM
1304 :     { beginCluster= beginCluster',
1305 :     endCluster = endCluster',
1306 :     emit = doStmt,
1307 :     pseudoOp = pseudoOp,
1308 :     defineLabel = defineLabel,
1309 :     entryLabel = entryLabel,
1310 :     comment = comment,
1311 :     annotation = annotation,
1312 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc),
1313 :     alias = alias,
1314 :     phi = phi
1315 :     }
1316 :    
1317 :     in self()
1318 : monnier 247 end
1319 :    
1320 : george 545 end (* functor *)
1321 :    
1322 :     end (* local *)

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