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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 :     structure X86MLTree : MLTREE
43 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
44 :     where I = X86Instr and T = X86MLTree
45 : monnier 475 sharing X86MLTree.Region = X86Instr.Region
46 : george 545 sharing X86MLTree.LabelExp = X86Instr.LabelExp
47 :     datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
48 :     val arch : arch ref
49 : leunga 593 val cvti2f :
50 :     (* source operand, guaranteed to be non-memory! *)
51 :     {ty: X86MLTree.ty, src: X86Instr.operand} ->
52 :     {instrs : X86Instr.instruction list,(* the instructions *)
53 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
54 :     cleanup: X86Instr.instruction list (* cleanup code *)
55 :     }
56 : leunga 731 (* When the following flag is set, we allocate floating point registers
57 :     * directly on the floating point stack
58 :     *)
59 :     val fast_floating_point : bool ref
60 : george 545 ) : sig include MLTREECOMP
61 :     val rewriteMemReg : bool
62 :     end =
63 : monnier 247 struct
64 :     structure T = X86MLTree
65 : monnier 429 structure S = T.Stream
66 : monnier 247 structure I = X86Instr
67 : george 545 structure C = I.C
68 :     structure Shuffle = Shuffle(I)
69 : monnier 247 structure W32 = Word32
70 : george 545 structure LE = I.LabelExp
71 :     structure A = MLRiscAnnotations
72 : monnier 247
73 : leunga 744 type instrStream = (I.instruction,C.cellset) T.stream
74 :     type mltreeStream = (T.stm,T.mlrisc list) T.stream
75 : leunga 565
76 :     datatype kind = REAL | INTEGER
77 : george 545
78 :     structure Gen = MLTreeGen
79 :     (structure T = T
80 :     val intTy = 32
81 :     val naturalWidths = [32]
82 :     datatype rep = SE | ZE | NEITHER
83 :     val rep = NEITHER
84 :     )
85 :    
86 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
87 : monnier 247
88 : george 545 (* Should we perform automatic MemReg translation?
89 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
90 :     *)
91 :     val rewriteMemReg = rewriteMemReg
92 : leunga 731
93 :     (* The following hardcoded *)
94 : leunga 744 fun isMemReg r = rewriteMemReg andalso
95 :     let val r = C.registerNum r
96 :     in r >= 8 andalso r < 32
97 :     end
98 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
99 : leunga 744 then let val r = C.registerNum r
100 :     in r >= 8 andalso r < 32 end
101 : leunga 731 else true
102 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
103 :     let val r = C.registerNum r
104 :     in r >= 8 andalso r < 32 end
105 :     )
106 : monnier 247
107 : george 555 val ST0 = C.ST 0
108 :     val ST7 = C.ST 7
109 :    
110 : george 545 (*
111 :     * The code generator
112 :     *)
113 : monnier 411 fun selectInstructions
114 : george 545 (instrStream as
115 :     S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,
116 : leunga 744 beginCluster,endCluster,exitBlock,comment,...}) =
117 : george 545 let exception EA
118 : monnier 411
119 : george 545 (* label where a trap is generated -- one per cluster *)
120 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
121 : monnier 247
122 : leunga 731 (* flag floating point generation *)
123 :     val floatingPointUsed = ref false
124 :    
125 : george 545 (* effective address of an integer register *)
126 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
127 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
128 : monnier 411
129 : george 545 (* Add an overflow trap *)
130 :     fun trap() =
131 :     let val jmp =
132 :     case !trapLabel of
133 :     NONE => let val label = Label.newLabel "trap"
134 :     val jmp = I.JCC{cond=I.O,
135 :     opnd=I.ImmedLabel(LE.LABEL label)}
136 :     in trapLabel := SOME(jmp, label); jmp end
137 :     | SOME(jmp, _) => jmp
138 :     in emit jmp end
139 : monnier 411
140 : george 545 val newReg = C.newReg
141 :     val newFreg = C.newFreg
142 : monnier 247
143 : leunga 731 fun fsize 32 = I.FP32
144 :     | fsize 64 = I.FP64
145 :     | fsize 80 = I.FP80
146 :     | fsize _ = error "fsize"
147 :    
148 : george 545 (* mark an expression with a list of annotations *)
149 :     fun mark'(i,[]) = i
150 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
151 : monnier 247
152 : george 545 (* annotate an expression and emit it *)
153 :     fun mark(i,an) = emit(mark'(i,an))
154 : monnier 247
155 : leunga 731 val emits = app emit
156 :    
157 : george 545 (* emit parallel copies for integers
158 :     * Translates parallel copies that involve memregs into
159 :     * individual copies.
160 :     *)
161 :     fun copy([], [], an) = ()
162 :     | copy(dst, src, an) =
163 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
164 : leunga 744 if C.sameColor(rd,rs) then [] else
165 : george 545 let val tmpR = I.Direct(newReg())
166 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
167 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
168 :     end
169 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
170 : leunga 744 if C.sameColor(rd,rs) then []
171 : george 545 else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
172 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
173 :     in
174 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
175 : leunga 744 {tmp=SOME(I.Direct(newReg())),
176 : george 545 dst=dst, src=src})
177 :     end
178 :    
179 :     (* conversions *)
180 :     val itow = Word.fromInt
181 :     val wtoi = Word.toInt
182 : george 761 fun toInt32 i = T.I.toInt32(32, i)
183 : george 545 val w32toi32 = Word32.toLargeIntX
184 :     val i32tow32 = Word32.fromLargeInt
185 : monnier 247
186 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
187 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
188 : monnier 247
189 : george 545 (* some useful registers *)
190 :     val eax = I.Direct(C.eax)
191 :     val ecx = I.Direct(C.ecx)
192 :     val edx = I.Direct(C.edx)
193 : monnier 247
194 : george 545 fun immedLabel lab = I.ImmedLabel(LE.LABEL lab)
195 :    
196 :     (* Is the expression zero? *)
197 : george 761 fun isZero(T.LI z) = T.I.isZero z
198 : george 545 | isZero(T.MARK(e,a)) = isZero e
199 :     | isZero _ = false
200 :     (* Does the expression set the zero bit?
201 :     * WARNING: we assume these things are not optimized out!
202 :     *)
203 :     fun setZeroBit(T.ANDB _) = true
204 :     | setZeroBit(T.ORB _) = true
205 :     | setZeroBit(T.XORB _) = true
206 :     | setZeroBit(T.SRA _) = true
207 :     | setZeroBit(T.SRL _) = true
208 :     | setZeroBit(T.SLL _) = true
209 : leunga 695 | setZeroBit(T.SUB _) = true
210 :     | setZeroBit(T.ADDT _) = true
211 :     | setZeroBit(T.SUBT _) = true
212 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
213 :     | setZeroBit _ = false
214 : monnier 247
215 : leunga 695 fun setZeroBit2(T.ANDB _) = true
216 :     | setZeroBit2(T.ORB _) = true
217 :     | setZeroBit2(T.XORB _) = true
218 :     | setZeroBit2(T.SRA _) = true
219 :     | setZeroBit2(T.SRL _) = true
220 :     | setZeroBit2(T.SLL _) = true
221 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
222 :     | setZeroBit2(T.SUB _) = true
223 :     | setZeroBit2(T.ADDT _) = true
224 :     | setZeroBit2(T.SUBT _) = true
225 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
226 :     | setZeroBit2 _ = false
227 :    
228 : leunga 731 (* emit parallel copies for floating point
229 :     * Normal version.
230 :     *)
231 :     fun fcopy'(fty, [], [], _) = ()
232 :     | fcopy'(fty, dst as [_], src as [_], an) =
233 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
234 : leunga 731 | fcopy'(fty, dst, src, an) =
235 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
236 : monnier 247
237 : leunga 731 (* emit parallel copies for floating point.
238 :     * Fast version.
239 :     * Translates parallel copies that involve memregs into
240 :     * individual copies.
241 :     *)
242 :    
243 :     fun fcopy''(fty, [], [], _) = ()
244 :     | fcopy''(fty, dst, src, an) =
245 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
246 :     let val fsize = fsize fty
247 :     fun mvInstr{dst, src} = [I.FMOVE{fsize=fsize, src=src, dst=dst}]
248 :     in
249 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
250 : leunga 744 {tmp=case dst of
251 : leunga 731 [_] => NONE
252 :     | _ => SOME(I.FPR(newReg())),
253 :     dst=dst, src=src})
254 :     end
255 :     else
256 :     mark(I.FCOPY{dst=dst,src=src,tmp=
257 :     case dst of
258 :     [_] => NONE
259 :     | _ => SOME(I.FPR(newFreg()))}, an)
260 :    
261 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
262 :     then fcopy'' x else fcopy' x
263 :    
264 : george 545 (* Translates MLTREE condition code to x86 condition code *)
265 :     fun cond T.LT = I.LT | cond T.LTU = I.B
266 :     | cond T.LE = I.LE | cond T.LEU = I.BE
267 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
268 :     | cond T.GE = I.GE | cond T.GEU = I.AE
269 :     | cond T.GT = I.GT | cond T.GTU = I.A
270 : monnier 247
271 : george 545 (* Move and annotate *)
272 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
273 : leunga 744 if C.sameColor(s,d) then ()
274 : george 545 else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
275 :     | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
276 : monnier 247
277 : george 545 (* Move only! *)
278 :     fun move(src, dst) = move'(src, dst, [])
279 : monnier 247
280 : george 545 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
281 : monnier 247
282 : george 545 val readonly = I.Region.readonly
283 : monnier 247
284 : george 545 (*
285 : george 761 * Compute an effective address.
286 : george 545 *)
287 : george 761 fun address(ea, mem) = let
288 : george 545 (* Keep building a bigger and bigger effective address expressions
289 :     * The input is a list of trees
290 :     * b -- base
291 :     * i -- index
292 :     * s -- scale
293 :     * d -- immed displacement
294 :     *)
295 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
296 :     | doEA(t::trees, b, i, s, d) =
297 :     (case t of
298 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
299 : george 545 | T.CONST c => doEALabel(trees, LE.CONST c, b, i, s, d)
300 :     | T.LABEL le => doEALabel(trees, le, b, i, s, d)
301 :     | T.ADD(32, t1, t2 as T.REG(_,r)) =>
302 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
303 :     else doEA(t1::t2::trees, b, i, s, d)
304 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
305 :     | T.SUB(32, t1, T.LI n) =>
306 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
307 :     | T.SLL(32, t1, T.LI n) => let
308 :     val n = T.I.toInt(32, n)
309 :     in
310 :     case n
311 :     of 0 => displace(trees, t1, b, i, s, d)
312 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
313 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
314 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
315 :     | _ => displace(trees, t, b, i, s, d)
316 :     end
317 : george 545 | t => displace(trees, t, b, i, s, d)
318 :     )
319 : monnier 247
320 : george 545 (* Add an immed constant *)
321 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
322 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
323 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
324 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
325 : george 761 doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,LE.INT(Int32.toInt n))))
326 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
327 : monnier 247
328 : george 545 (* Add a label expression *)
329 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
330 :     doEA(trees, b, i, s, I.ImmedLabel le)
331 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
332 :     doEA(trees, b, i, s,
333 :     I.ImmedLabel(LE.PLUS(le,LE.INT(Int32.toInt m)))
334 :     handle Overflow => error "doEALabel: constant too large")
335 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
336 :     doEA(trees, b, i, s, I.ImmedLabel(LE.PLUS(le,le')))
337 :     | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
338 : monnier 247
339 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
340 :     | makeAddressingMode(SOME base, NONE, _, disp) =
341 :     I.Displace{base=base, disp=disp, mem=mem}
342 :     | makeAddressingMode(base, SOME index, scale, disp) =
343 : george 761 I.Indexed{base=base, index=index, scale=scale,
344 : george 545 disp=disp, mem=mem}
345 : monnier 247
346 : george 545 (* generate code for tree and ensure that it is not in %esp *)
347 :     and exprNotEsp tree =
348 :     let val r = expr tree
349 : leunga 744 in if C.sameColor(r, C.esp) then
350 : george 545 let val tmp = newReg()
351 :     in move(I.Direct r, I.Direct tmp); tmp end
352 :     else r
353 :     end
354 : monnier 247
355 : george 545 (* Add a base register *)
356 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
357 :     doEA(trees, SOME(expr t), i, s, d)
358 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
359 :     (* make t the index, but make sure that it is not %esp! *)
360 :     let val i = expr t
361 : leunga 744 in if C.sameColor(i, C.esp) then
362 : george 545 (* swap base and index *)
363 : leunga 744 if C.sameColor(base, C.esp) then
364 : george 545 doEA(trees, SOME i, b, 0, d)
365 :     else (* base and index = %esp! *)
366 :     let val index = newReg()
367 :     in move(I.Direct i, I.Direct index);
368 :     doEA(trees, b, SOME index, 0, d)
369 :     end
370 :     else
371 :     doEA(trees, b, SOME i, 0, d)
372 :     end
373 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
374 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
375 :     in doEA(trees, SOME b, i, s, d) end
376 : monnier 247
377 : george 545 (* Add an indexed register *)
378 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
379 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
380 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
381 :     doEA(trees, SOME(expr t0), i, s, d)
382 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
383 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
384 :     in doEA(trees, SOME b, i, s, d) end
385 :    
386 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
387 :     I.Immed _ => raise EA
388 :     | I.ImmedLabel le => I.LabelEA le
389 :     | ea => ea
390 :     end (* address *)
391 : monnier 247
392 : george 545 (* reduce an expression into an operand *)
393 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
394 : george 545 | operand(T.CONST c) = I.ImmedLabel(LE.CONST c)
395 :     | operand(T.LABEL lab) = I.ImmedLabel lab
396 :     | operand(T.REG(_,r)) = IntReg r
397 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
398 :     | operand(t) = I.Direct(expr t)
399 : monnier 247
400 : george 545 and moveToReg(opnd) =
401 :     let val dst = I.Direct(newReg())
402 :     in move(opnd, dst); dst
403 :     end
404 : monnier 247
405 : george 545 and reduceOpnd(I.Direct r) = r
406 :     | reduceOpnd opnd =
407 :     let val dst = newReg()
408 :     in move(opnd, I.Direct dst); dst
409 :     end
410 : monnier 247
411 : george 545 (* ensure that the operand is either an immed or register *)
412 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
413 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
414 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
415 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
416 :     | immedOrReg opnd = opnd
417 : monnier 247
418 : george 545 and isImmediate(I.Immed _) = true
419 :     | isImmediate(I.ImmedLabel _) = true
420 :     | isImmediate _ = false
421 : monnier 247
422 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
423 :    
424 :     and isMemOpnd opnd =
425 :     (case opnd of
426 :     I.Displace _ => true
427 :     | I.Indexed _ => true
428 :     | I.MemReg _ => true
429 :     | I.LabelEA _ => true
430 : george 555 | I.FDirect f => true
431 : george 545 | _ => false
432 :     )
433 :    
434 :     (*
435 :     * Compute an integer expression and put the result in
436 :     * the destination register rd.
437 :     *)
438 :     and doExpr(exp, rd : I.C.cell, an) =
439 :     let val rdOpnd = IntReg rd
440 : monnier 247
441 : leunga 744 fun equalRd(I.Direct r) = C.sameColor(r, rd)
442 :     | equalRd(I.MemReg r) = C.sameColor(r, rd)
443 : george 545 | equalRd _ = false
444 : monnier 247
445 : george 545 (* Emit a binary operator. If the destination is
446 :     * a memReg, do something smarter.
447 :     *)
448 :     fun genBinary(binOp, opnd1, opnd2) =
449 :     if isMemReg rd andalso
450 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
451 :     equalRd(opnd2)
452 :     then
453 :     let val tmpR = newReg()
454 :     val tmp = I.Direct tmpR
455 :     in move(opnd1, tmp);
456 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
457 :     move(tmp, rdOpnd)
458 :     end
459 :     else
460 :     (move(opnd1, rdOpnd);
461 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
462 :     )
463 : monnier 247
464 : george 545 (* Generate a binary operator; it may commute *)
465 :     fun binaryComm(binOp, e1, e2) =
466 :     let val (opnd1, opnd2) =
467 :     case (operand e1, operand e2) of
468 :     (x as I.Immed _, y) => (y, x)
469 :     | (x as I.ImmedLabel _, y) => (y, x)
470 :     | (x, y as I.Direct _) => (y, x)
471 :     | (x, y) => (x, y)
472 :     in genBinary(binOp, opnd1, opnd2)
473 :     end
474 :    
475 :     (* Generate a binary operator; non-commutative *)
476 :     fun binary(binOp, e1, e2) =
477 :     genBinary(binOp, operand e1, operand e2)
478 :    
479 :     (* Generate a unary operator *)
480 :     fun unary(unOp, e) =
481 :     let val opnd = operand e
482 :     in if isMemReg rd andalso isMemOpnd opnd then
483 :     let val tmp = I.Direct(newReg())
484 :     in move(opnd, tmp); move(tmp, rdOpnd)
485 :     end
486 :     else move(opnd, rdOpnd);
487 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
488 :     end
489 :    
490 :     (* Generate shifts; the shift
491 :     * amount must be a constant or in %ecx *)
492 :     fun shift(opcode, e1, e2) =
493 :     let val (opnd1, opnd2) = (operand e1, operand e2)
494 :     in case opnd2 of
495 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
496 :     | _ =>
497 :     if equalRd(opnd2) then
498 :     let val tmpR = newReg()
499 :     val tmp = I.Direct tmpR
500 :     in move(opnd1, tmp);
501 :     move(opnd2, ecx);
502 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
503 :     move(tmp, rdOpnd)
504 :     end
505 :     else
506 :     (move(opnd1, rdOpnd);
507 :     move(opnd2, ecx);
508 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
509 :     )
510 :     end
511 :    
512 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
513 :     fun divrem(signed, overflow, e1, e2, resultReg) =
514 :     let val (opnd1, opnd2) = (operand e1, operand e2)
515 :     val _ = move(opnd1, eax)
516 : leunga 606 val oper = if signed then (emit(I.CDQ); I.IDIVL)
517 :     else (zero edx; I.DIVL)
518 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
519 :     move(resultReg, rdOpnd);
520 :     if overflow then trap() else ()
521 :     end
522 :    
523 :     (* Optimize the special case for division *)
524 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
525 :     val n = toInt32 n'
526 :     val w = T.I.toWord32(32, n')
527 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
528 : george 545 fun log2 n = (* n must be > 0!!! *)
529 :     let fun loop(0w1,pow) = pow
530 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
531 : george 545 in loop(n,0) end
532 :     in if n > 1 andalso isPowerOf2 w then
533 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
534 : george 545 in if signed then
535 :     (* signed; simulate round towards zero *)
536 :     let val label = Label.newLabel ""
537 :     val reg1 = expr e1
538 :     val opnd1 = I.Direct reg1
539 :     in if setZeroBit e1 then ()
540 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
541 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
542 :     emit(if n = 2 then
543 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
544 :     else
545 :     I.BINARY{binOp=I.ADDL,
546 : george 761 src=I.Immed(n - 1),
547 : george 545 dst=opnd1});
548 :     defineLabel label;
549 :     shift(I.SARL, T.REG(32, reg1), pow)
550 :     end
551 :     else (* unsigned *)
552 :     shift(I.SHRL, e1, pow)
553 :     end
554 :     else
555 :     (* note the only way we can overflow is if
556 :     * n = 0 or n = -1
557 :     *)
558 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
559 :     e1, e2, eax)
560 :     end
561 :     | divide(signed, overflow, e1, e2) =
562 :     divrem(signed, overflow, e1, e2, eax)
563 : monnier 247
564 : george 545 fun rem(signed, overflow, e1, e2) =
565 :     divrem(signed, overflow, e1, e2, edx)
566 :    
567 :     (* unsigned integer multiplication *)
568 :     fun uMultiply(e1, e2) =
569 :     (* note e2 can never be (I.Direct edx) *)
570 :     (move(operand e1, eax);
571 : leunga 606 mark(I.MULTDIV{multDivOp=I.MULL,
572 : george 545 src=regOrMem(operand e2)},an);
573 :     move(eax, rdOpnd)
574 :     )
575 :    
576 :     (* signed integer multiplication:
577 :     * The only forms that are allowed that also sets the
578 :     * OF and CF flags are:
579 :     *
580 :     * imul r32, r32/m32, imm8
581 :     * imul r32, imm8
582 :     * imul r32, imm32
583 :     *)
584 :     fun multiply(e1, e2) =
585 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _, dstR, dst) =
586 :     (move(i1, dst);
587 :     mark(I.MUL3{dst=dstR, src1=i2, src2=NONE},an))
588 :     | doit(rm, i2 as I.Immed _, dstR, dst) =
589 :     doit(i2, rm, dstR, dst)
590 :     | doit(imm as I.Immed(i), rm, dstR, dst) =
591 :     mark(I.MUL3{dst=dstR, src1=rm, src2=SOME i},an)
592 :     | doit(r1 as I.Direct _, r2 as I.Direct _, dstR, dst) =
593 :     (move(r1, dst);
594 :     mark(I.MUL3{dst=dstR, src1=r2, src2=NONE},an))
595 :     | doit(r1 as I.Direct _, rm, dstR, dst) =
596 :     (move(r1, dst);
597 :     mark(I.MUL3{dst=dstR, src1=rm, src2=NONE},an))
598 :     | doit(rm, r as I.Direct _, dstR, dst) =
599 :     doit(r, rm, dstR, dst)
600 :     | doit(rm1, rm2, dstR, dst) =
601 :     if equalRd rm2 then
602 :     let val tmpR = newReg()
603 :     val tmp = I.Direct tmpR
604 :     in move(rm1, tmp);
605 :     mark(I.MUL3{dst=tmpR, src1=rm2, src2=NONE},an);
606 :     move(tmp, dst)
607 :     end
608 :     else
609 :     (move(rm1, dst);
610 :     mark(I.MUL3{dst=dstR, src1=rm2, src2=NONE},an)
611 :     )
612 :     val (opnd1, opnd2) = (operand e1, operand e2)
613 :     in if isMemReg rd then (* destination must be a real reg *)
614 :     let val tmpR = newReg()
615 :     val tmp = I.Direct tmpR
616 :     in doit(opnd1, opnd2, tmpR, tmp);
617 :     move(tmp, rdOpnd)
618 :     end
619 :     else
620 :     doit(opnd1, opnd2, rd, rdOpnd)
621 :     end
622 : monnier 247
623 : george 545 (* Makes sure the destination must be a register *)
624 :     fun dstMustBeReg f =
625 :     if isMemReg rd then
626 :     let val tmpR = newReg()
627 :     val tmp = I.Direct(tmpR)
628 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
629 :     else f(rd, rdOpnd)
630 : monnier 247
631 : george 545 (* Emit a load instruction; makes sure that the destination
632 :     * is a register
633 :     *)
634 :     fun genLoad(mvOp, ea, mem) =
635 :     dstMustBeReg(fn (_, dst) =>
636 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
637 :    
638 :     (* Generate a zero extended loads *)
639 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
640 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
641 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
642 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
643 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
644 :    
645 :     (* Generate a sign extended loads *)
646 :    
647 :     (* Generate setcc instruction:
648 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
649 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
650 :     * Note that we have to use eax as the destination of the
651 :     * setcc because it only works on the registers
652 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
653 :     * are inaccessible in 32 bit mode.
654 : george 545 *)
655 :     fun setcc(ty, cc, t1, t2, yes, no) =
656 : leunga 583 let val (cc, yes, no) =
657 :     if yes > no then (cc, yes, no)
658 :     else (T.Basis.negateCond cc, no, yes)
659 : george 545 in (* Clear the destination first.
660 :     * This this because stupid SETcc
661 :     * only writes to the low order
662 :     * byte. That's Intel architecture, folks.
663 :     *)
664 : leunga 695 case (yes, no, cc) of
665 :     (1, 0, T.LT) =>
666 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
667 :     in move(tmp, rdOpnd);
668 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
669 :     end
670 :     | (1, 0, T.GT) =>
671 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
672 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
673 :     move(tmp, rdOpnd);
674 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
675 :     end
676 :     | (1, 0, _) => (* normal case *)
677 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
678 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
679 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
680 : leunga 583 move(eax, rdOpnd)
681 :     end
682 : leunga 695 | (C1, C2, _) =>
683 : george 545 (* general case;
684 : leunga 583 * from the Intel optimization guide p3-5
685 :     *)
686 : leunga 695 let val _ = zero eax;
687 :     val cc = cmp(true, ty, cc, t1, t2, [])
688 : leunga 583 in case C1-C2 of
689 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
690 :     let val (base,scale) =
691 :     case D of
692 :     1 => (NONE, 0)
693 :     | 2 => (NONE, 1)
694 :     | 3 => (SOME C.eax, 1)
695 :     | 4 => (NONE, 2)
696 :     | 5 => (SOME C.eax, 2)
697 :     | 8 => (NONE, 3)
698 :     | 9 => (SOME C.eax, 3)
699 :     val addr = I.Indexed{base=base,
700 :     index=C.eax,
701 :     scale=scale,
702 :     disp=I.Immed C2,
703 : george 545 mem=readonly}
704 : leunga 583 val tmpR = newReg()
705 :     val tmp = I.Direct tmpR
706 :     in emit(I.SET{cond=cond cc, opnd=eax});
707 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
708 :     move(tmp, rdOpnd)
709 :     end
710 :     | D =>
711 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
712 :     opnd=eax});
713 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
714 :     emit(I.BINARY{binOp=I.ANDL,
715 :     src=I.Immed D, dst=eax});
716 :     if C2 = 0 then
717 :     move(eax, rdOpnd)
718 :     else
719 :     let val tmpR = newReg()
720 :     val tmp = I.Direct tmpR
721 :     in mark(I.LEA{addr=
722 :     I.Displace{
723 :     base=C.eax,
724 :     disp=I.Immed C2,
725 :     mem=readonly},
726 :     r32=tmpR}, an);
727 :     move(tmp, rdOpnd)
728 :     end
729 :     )
730 :     end
731 : george 545 end (* setcc *)
732 :    
733 :     (* Generate cmovcc instruction.
734 :     * on Pentium Pro and Pentium II only
735 :     *)
736 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
737 :     let fun genCmov(dstR, _) =
738 :     let val _ = doExpr(no, dstR, []) (* false branch *)
739 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
740 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
741 :     end
742 :     in dstMustBeReg genCmov
743 :     end
744 :    
745 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
746 : monnier 247
747 : leunga 606 (* Add n to rd *)
748 :     fun addN n =
749 :     let val n = operand n
750 :     val src = if isMemReg rd then immedOrReg n else n
751 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
752 :    
753 : george 545 (* Generate addition *)
754 :     fun addition(e1, e2) =
755 : leunga 606 case e1 of
756 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e2
757 :     else addition1(e1,e2)
758 : leunga 606 | _ => addition1(e1,e2)
759 :     and addition1(e1, e2) =
760 :     case e2 of
761 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e1
762 :     else addition2(e1,e2)
763 : leunga 606 | _ => addition2(e1,e2)
764 :     and addition2(e1,e2) =
765 : george 545 (dstMustBeReg(fn (dstR, _) =>
766 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
767 :     handle EA => binaryComm(I.ADDL, e1, e2))
768 : monnier 247
769 :    
770 : george 545 in case exp of
771 :     T.REG(_,rs) =>
772 :     if isMemReg rs andalso isMemReg rd then
773 :     let val tmp = I.Direct(newReg())
774 : leunga 731 in move'(I.MemReg rs, tmp, an);
775 : george 545 move'(tmp, rdOpnd, [])
776 :     end
777 :     else move'(IntReg rs, rdOpnd, an)
778 : george 761 | T.LI z => let
779 :     val n = toInt32 z
780 :     in
781 :     if n=0 then
782 :     (* As per Fermin's request, special optimization for rd := 0.
783 :     * Currently we don't bother with the size.
784 :     *)
785 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
786 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
787 :     else
788 :     move'(I.Immed(n), rdOpnd, an)
789 :     end
790 : george 545 | T.CONST c => move'(I.ImmedLabel(LE.CONST c), rdOpnd, an)
791 :     | T.LABEL lab => move'(I.ImmedLabel lab, rdOpnd, an)
792 : monnier 247
793 : george 545 (* 32-bit addition *)
794 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
795 :     val n = toInt32 n
796 :     in
797 :     case n
798 :     of 1 => unary(I.INCL, e1)
799 :     | ~1 => unary(I.DECL, e1)
800 :     | _ => addition(e1, e2)
801 :     end
802 :     | T.ADD(32, e1 as T.LI n, e2) => let
803 :     val n = toInt32 n
804 :     in
805 :     case n
806 :     of 1 => unary(I.INCL, e2)
807 :     | ~1 => unary(I.DECL, e2)
808 :     | _ => addition(e1, e2)
809 :     end
810 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
811 : monnier 247
812 : leunga 695 (* 32-bit addition but set the flag!
813 :     * This is a stupid hack for now.
814 :     *)
815 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
816 :     val n = T.I.toInt(32, n)
817 :     in
818 :     if n=1 then unary(I.INCL, e)
819 :     else if n = ~1 then unary(I.DECL, e)
820 :     else binaryComm(I.ADDL, e, e1)
821 :     end
822 :     | T.ADD(0, e1 as T.LI n, e) => let
823 :     val n = T.I.toInt(32, n)
824 :     in
825 :     if n=1 then unary(I.INCL, e)
826 :     else if n = ~1 then unary(I.DECL, e)
827 :     else binaryComm(I.ADDL, e1, e)
828 :     end
829 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
830 :    
831 : george 545 (* 32-bit subtraction *)
832 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
833 :     val n = toInt32 n
834 :     in
835 :     case n
836 :     of 0 => doExpr(e1, rd, an)
837 :     | 1 => unary(I.DECL, e1)
838 :     | ~1 => unary(I.INCL, e1)
839 :     | _ => binary(I.SUBL, e1, e2)
840 :     end
841 :     | T.SUB(32, e1 as T.LI n, e2) =>
842 :     if T.I.isZero n then unary(I.NEGL, e2)
843 :     else binary(I.SUBL, e1, e2)
844 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
845 : monnier 247
846 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
847 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
848 :     | T.REMU(32, x, y) => rem(false, false, x, y)
849 : monnier 247
850 : george 545 | T.MULS(32, x, y) => multiply(x, y)
851 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
852 :     | T.REMS(32, x, y) => rem(true, false, x, y)
853 : monnier 247
854 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
855 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
856 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
857 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
858 :     | T.REMT(32, x, y) => rem(true, true, x, y)
859 : monnier 247
860 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
861 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
862 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
863 :     | T.NOTB(32, x) => unary(I.NOTL, x)
864 : monnier 247
865 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
866 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
867 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
868 : monnier 247
869 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
870 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
871 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
872 : leunga 744 | T.SX(_,_,T.LOAD(8,ea,mem)) => load8s(ea, mem)
873 :     | T.SX(_,_,T.LOAD(16,ea,mem)) => load16s(ea, mem)
874 : monnier 498
875 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
876 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
877 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
878 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
879 :     Pentium => unknownExp exp
880 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
881 :     )
882 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
883 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
884 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
885 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
886 : george 555 | T.REXT e =>
887 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
888 : george 545 (* simplify and try again *)
889 :     | exp => unknownExp exp
890 :     end (* doExpr *)
891 : monnier 247
892 : george 545 (* generate an expression and return its result register
893 :     * If rewritePseudo is on, the result is guaranteed to be in a
894 :     * non memReg register
895 :     *)
896 :     and expr(exp as T.REG(_, rd)) =
897 :     if isMemReg rd then genExpr exp else rd
898 :     | expr exp = genExpr exp
899 : monnier 247
900 : george 545 and genExpr exp =
901 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
902 : monnier 247
903 : george 545 (* Compare an expression with zero.
904 :     * On the x86, TEST is superior to AND for doing the same thing,
905 :     * since it doesn't need to write out the result in a register.
906 :     *)
907 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
908 : george 545 (case ty of
909 : leunga 695 8 => test(I.TESTB, a, b, an)
910 :     | 16 => test(I.TESTW, a, b, an)
911 :     | 32 => test(I.TESTL, a, b, an)
912 :     | _ => doExpr(e, newReg(), an);
913 :     cc)
914 :     | cmpWithZero(cc, e, an) =
915 :     let val e =
916 :     case e of (* hack to disable the lea optimization XXX *)
917 :     T.ADD(_, a, b) => T.ADD(0, a, b)
918 :     | e => e
919 :     in doExpr(e, newReg(), an); cc end
920 : monnier 247
921 : george 545 (* Emit a test.
922 :     * The available modes are
923 :     * r/m, r
924 :     * r/m, imm
925 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
926 :     * When anding an operand with a constant
927 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
928 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
929 :     * this works for memory operands too. However, with TESTB, it is
930 :     * not possible to use registers other than
931 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
932 :     * perform register allocation first, and if the operand registers
933 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
934 :     * by TESTB.
935 :     *)
936 : leunga 695 and test(testopcode, a, b, an) =
937 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
938 :     (* translate r, r/m => r/m, r *)
939 :     val (opnd1, opnd2) =
940 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
941 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
942 : george 545 end
943 : monnier 247
944 : george 545 (* generate a condition code expression
945 : leunga 744 * The zero is for setting the condition code!
946 :     * I have no idea why this is used.
947 :     *)
948 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
949 :     if C.sameColor(rd, C.eflags) then
950 :     (cmp(false, ty, cc, t1, t2, an); ())
951 :     else
952 :     error "doCCexpr: cmp"
953 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
954 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
955 :     | doCCexpr(T.CCEXT e, cd, an) =
956 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
957 : george 545 | doCCexpr _ = error "doCCexpr"
958 : monnier 247
959 : george 545 and ccExpr e = error "ccExpr"
960 : monnier 247
961 : george 545 (* generate a comparison and sets the condition code;
962 :     * return the actual cc used. If the flag swapable is true,
963 :     * we can also reorder the operands.
964 :     *)
965 :     and cmp(swapable, ty, cc, t1, t2, an) =
966 : leunga 695 (* == and <> can be always be reordered *)
967 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
968 :     in (* Sometimes the comparison is not necessary because
969 :     * the bits are already set!
970 :     *)
971 :     if isZero t1 andalso setZeroBit2 t2 then
972 :     if swapable then
973 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
974 :     else (* can't reorder the comparison! *)
975 :     genCmp(ty, false, cc, t1, t2, an)
976 :     else if isZero t2 andalso setZeroBit2 t1 then
977 :     cmpWithZero(cc, t1, an)
978 :     else genCmp(ty, swapable, cc, t1, t2, an)
979 :     end
980 : monnier 247
981 : george 545 (* Give a and b which are the operands to a comparison (or test)
982 :     * Return the appropriate condition code and operands.
983 :     * The available modes are:
984 :     * r/m, imm
985 :     * r/m, r
986 :     * r, r/m
987 :     *)
988 :     and commuteComparison(cc, swapable, a, b) =
989 :     let val (opnd1, opnd2) = (operand a, operand b)
990 :     in (* Try to fold in the operands whenever possible *)
991 :     case (isImmediate opnd1, isImmediate opnd2) of
992 :     (true, true) => (cc, moveToReg opnd1, opnd2)
993 :     | (true, false) =>
994 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
995 :     else (cc, moveToReg opnd1, opnd2)
996 :     | (false, true) => (cc, opnd1, opnd2)
997 :     | (false, false) =>
998 :     (case (opnd1, opnd2) of
999 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1000 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1001 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1002 :     )
1003 :     end
1004 :    
1005 :     (* generate a real comparison; return the real cc used *)
1006 :     and genCmp(ty, swapable, cc, a, b, an) =
1007 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1008 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1009 :     end
1010 : monnier 247
1011 : george 545 (* generate code for jumps *)
1012 :     and jmp(T.LABEL(lexp as LE.LABEL lab), labs, an) =
1013 :     mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1014 :     | jmp(T.LABEL lexp, labs, an) = mark(I.JMP(I.ImmedLabel lexp, labs), an)
1015 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1016 :    
1017 :     (* convert mlrisc to cellset:
1018 :     *)
1019 :     and cellset mlrisc =
1020 : leunga 744 let val addCCReg = C.CellSet.add
1021 : george 545 fun g([],acc) = acc
1022 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1023 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1024 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1025 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1026 :     | g(_::regs, acc) = g(regs, acc)
1027 :     in g(mlrisc, C.empty) end
1028 :    
1029 :     (* generate code for calls *)
1030 :     and call(ea, flow, def, use, mem, an) =
1031 :     mark(I.CALL(operand ea,cellset(def),cellset(use),mem),an)
1032 :    
1033 :     (* generate code for integer stores *)
1034 :     and store8(ea, d, mem, an) =
1035 :     let val src = (* movb has to use %eax as source. Stupid x86! *)
1036 :     case immedOrReg(operand d) of
1037 :     src as I.Direct r =>
1038 : leunga 744 if C.sameColor(r,C.eax)
1039 :     then src else (move(src, eax); eax)
1040 : george 545 | src => src
1041 :     in mark(I.MOVE{mvOp=I.MOVB, src=src, dst=address(ea,mem)},an)
1042 :     end
1043 :     and store16(ea, d, mem, an) = error "store16"
1044 :     and store32(ea, d, mem, an) =
1045 :     move'(immedOrReg(operand d), address(ea, mem), an)
1046 :    
1047 :     (* generate code for branching *)
1048 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1049 :     (* allow reordering of operands *)
1050 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1051 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1052 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1053 :     fbranch(fty, fcc, t1, t2, lab, an)
1054 :     | branch(ccexp, lab, an) =
1055 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1056 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1057 :     )
1058 :    
1059 :     (* generate code for floating point compare and branch *)
1060 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1061 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1062 :     | ignoreOrder (T.FLOAD _) = true
1063 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1064 :     | ignoreOrder _ = false
1065 :    
1066 :     fun compare'() = (* Sethi-Ullman style *)
1067 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1068 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1069 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1070 :     emit(I.FXCH{opnd=C.ST(1)}));
1071 :     emit(I.FUCOMPP);
1072 :     fcc
1073 :     )
1074 :    
1075 :     fun compare''() =
1076 :     (* direct style *)
1077 :     (* Try to make lsrc the memory operand *)
1078 :     let val lsrc = foperand(fty, t1)
1079 :     val rsrc = foperand(fty, t2)
1080 :     val fsize = fsize fty
1081 :     fun cmp(lsrc, rsrc, fcc) =
1082 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1083 :     in case (lsrc, rsrc) of
1084 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1085 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1086 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1087 :     | (lsrc, rsrc) => (* can't be both memory! *)
1088 :     let val ftmpR = newFreg()
1089 :     val ftmp = I.FPR ftmpR
1090 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1091 :     cmp(lsrc, ftmp, fcc)
1092 :     end
1093 :     end
1094 :    
1095 :     fun compare() =
1096 :     if enableFastFPMode andalso !fast_floating_point
1097 :     then compare''() else compare'()
1098 :    
1099 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1100 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1101 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1102 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1103 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1104 :     fun sahf() = emit(I.SAHF)
1105 : leunga 731 fun branch(fcc) =
1106 : george 545 case fcc
1107 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1108 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1109 :     | T.? => (sahf(); j(I.P,lab))
1110 :     | T.<=> => (sahf(); j(I.NP,lab))
1111 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1112 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1113 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1114 :     | T.?< => (testil 0x500; j(I.NE,lab))
1115 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1116 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1117 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1118 :     cmpil 0x4000; j(I.EQ,lab))
1119 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1120 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1121 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1122 : george 545 | _ => error "fbranch"
1123 :     (*esac*)
1124 : leunga 731 val fcc = compare()
1125 :     in emit I.FNSTSW;
1126 :     branch(fcc)
1127 : monnier 411 end
1128 : monnier 247
1129 : leunga 731 (*========================================================
1130 :     * Floating point code generation starts here.
1131 :     * Some generic fp routines first.
1132 :     *========================================================*)
1133 :    
1134 :     (* Can this tree be folded into the src operand of a floating point
1135 :     * operations?
1136 :     *)
1137 :     and foldableFexp(T.FREG _) = true
1138 :     | foldableFexp(T.FLOAD _) = true
1139 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1140 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1141 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1142 :     | foldableFexp _ = false
1143 :    
1144 :     (* Move integer e of size ty into a memory location.
1145 :     * Returns a quadruple:
1146 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1147 :     *)
1148 :     and convertIntToFloat(ty, e) =
1149 :     let val opnd = operand e
1150 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1151 :     then (INTEGER, ty, opnd, [])
1152 :     else
1153 :     let val {instrs, tempMem, cleanup} = cvti2f{ty=ty, src=opnd}
1154 :     in emits instrs;
1155 :     (INTEGER, 32, tempMem, cleanup)
1156 :     end
1157 :     end
1158 :    
1159 :     (*========================================================
1160 :     * Sethi-Ullman based floating point code generation as
1161 :     * implemented by Lal
1162 :     *========================================================*)
1163 :    
1164 : george 545 and fld(32, opnd) = I.FLDS opnd
1165 :     | fld(64, opnd) = I.FLDL opnd
1166 : george 555 | fld(80, opnd) = I.FLDT opnd
1167 : george 545 | fld _ = error "fld"
1168 :    
1169 : leunga 565 and fild(16, opnd) = I.FILD opnd
1170 :     | fild(32, opnd) = I.FILDL opnd
1171 :     | fild(64, opnd) = I.FILDLL opnd
1172 :     | fild _ = error "fild"
1173 :    
1174 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1175 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1176 :    
1177 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1178 :     | fstp(64, opnd) = I.FSTPL opnd
1179 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1180 : george 545 | fstp _ = error "fstp"
1181 :    
1182 :     (* generate code for floating point stores *)
1183 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1184 : george 545 (case d of
1185 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1186 :     | _ => reduceFexp(fty, d, []);
1187 :     mark(fstp(fty, address(ea, mem)), an)
1188 :     )
1189 :    
1190 : leunga 731 (* generate code for floating point loads *)
1191 :     and fload'(fty, ea, mem, fd, an) =
1192 :     let val ea = address(ea, mem)
1193 :     in mark(fld(fty, ea), an);
1194 : leunga 744 if C.sameColor(fd,ST0) then ()
1195 :     else emit(fstp(fty, I.FDirect fd))
1196 : leunga 731 end
1197 :    
1198 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1199 : george 545
1200 :     (* generate floating point expression and put the result in fd *)
1201 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1202 : leunga 744 (if C.sameColor(fs,fd) then ()
1203 : george 545 else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
1204 :     )
1205 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1206 :     fload'(fty, ea, mem, fd, an)
1207 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1208 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1209 : leunga 744 if C.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1210 : leunga 731 )
1211 :     | doFexpr'(fty, e, fd, an) =
1212 : george 545 (reduceFexp(fty, e, []);
1213 : leunga 744 if C.sameColor(fd,ST0) then ()
1214 :     else mark(fstp(fty, I.FDirect fd), an)
1215 : george 545 )
1216 :    
1217 :     (*
1218 :     * Generate floating point expression using Sethi-Ullman's scheme:
1219 :     * This function evaluates a floating point expression,
1220 :     * and put result in %ST(0).
1221 :     *)
1222 :     and reduceFexp(fty, fexp, an) =
1223 : george 555 let val ST = I.ST(C.ST 0)
1224 :     val ST1 = I.ST(C.ST 1)
1225 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1226 : george 545
1227 : leunga 565 datatype su_tree =
1228 :     LEAF of int * T.fexp * ans
1229 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1230 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1231 :     and fbinop = FADD | FSUB | FMUL | FDIV
1232 :     | FIADD | FISUB | FIMUL | FIDIV
1233 :     withtype ans = Annotations.annotations
1234 : monnier 247
1235 : leunga 565 fun label(LEAF(n, _, _)) = n
1236 :     | label(BINARY(n, _, _, _, _, _)) = n
1237 :     | label(UNARY(n, _, _, _, _)) = n
1238 : george 545
1239 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1240 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1241 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1242 : george 545
1243 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1244 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1245 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1246 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1247 :     | su(T.CVTF2F(_, _, t)) = su t
1248 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1249 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1250 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1251 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1252 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1253 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1254 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1255 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1256 :     | su _ = error "su"
1257 :    
1258 :     (* Try to fold the the memory operand or integer conversion *)
1259 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1260 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1261 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1262 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1263 :     | suFold(T.FMARK(t, a)) =
1264 :     let val (t, integer) = suFold t
1265 :     in (annotate(t, a), integer) end
1266 :     | suFold e = (su e, false)
1267 :    
1268 :     (* Form unary tree *)
1269 :     and suUnary(fty, funary, t) =
1270 :     let val t = su t
1271 :     in UNARY(label t, fty, funary, t, [])
1272 : george 545 end
1273 : leunga 565
1274 :     (* Form binary tree *)
1275 :     and suBinary(fty, binop, ibinop, t1, t2) =
1276 :     let val t1 = su t1
1277 :     val (t2, integer) = suFold t2
1278 :     val n1 = label t1
1279 :     val n2 = label t2
1280 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1281 :     val myOp = if integer then ibinop else binop
1282 :     in BINARY(n, fty, myOp, t1, t2, [])
1283 : george 545 end
1284 : george 555
1285 : leunga 565 (* Try to fold in the operand if possible.
1286 :     * This only applies to commutative operations.
1287 :     *)
1288 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1289 : leunga 731 let val (t1, t2) = if foldableFexp t2
1290 :     then (t1, t2) else (t2, t1)
1291 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1292 :    
1293 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1294 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1295 :     t1 = t2 andalso C.sameColor(f1,f2)
1296 : leunga 565 | sameTree _ = false
1297 :    
1298 :     (* Traverse tree and generate code *)
1299 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1300 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1301 :     let val _ = gencode x
1302 :     val (_, fty, src) = leafEA y
1303 :     fun gen(code) = mark(code, a1 @ a2)
1304 :     fun binary(oper32, oper64) =
1305 :     if sameTree(x, t2) then
1306 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1307 : george 555 else
1308 :     let val oper =
1309 : leunga 565 if isMemOpnd src then
1310 :     case fty of
1311 :     32 => oper32
1312 :     | 64 => oper64
1313 :     | _ => error "gencode: BINARY"
1314 :     else oper64
1315 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1316 :     fun ibinary(oper16, oper32) =
1317 :     let val oper = case fty of
1318 :     16 => oper16
1319 :     | 32 => oper32
1320 :     | _ => error "gencode: IBINARY"
1321 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1322 :     in case binop of
1323 :     FADD => binary(I.FADDS, I.FADDL)
1324 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1325 :     | FMUL => binary(I.FMULS, I.FMULL)
1326 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1327 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1328 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1329 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1330 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1331 :     end
1332 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1333 :     let fun doit(t1, t2, oper, operP, operRP) =
1334 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1335 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1336 :     *)
1337 :     val n1 = label t1
1338 :     val n2 = label t2
1339 :     in if n1 < n2 andalso n1 <= 7 then
1340 :     (gencode t2;
1341 :     gencode t1;
1342 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1343 :     else if n2 <= n1 andalso n2 <= 7 then
1344 :     (gencode t1;
1345 :     gencode t2;
1346 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1347 :     else
1348 :     let (* both labels > 7 *)
1349 :     val fs = I.FDirect(newFreg())
1350 :     in gencode t2;
1351 :     emit(fstp(fty, fs));
1352 :     gencode t1;
1353 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1354 :     end
1355 :     end
1356 :     in case binop of
1357 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1358 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1359 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1360 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1361 : george 545 | _ => error "gencode.BINARY"
1362 :     end
1363 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1364 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1365 :    
1366 :     (* Generate code for a leaf.
1367 :     * Returns the type and an effective address
1368 :     *)
1369 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1370 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1371 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1372 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1373 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1374 : leunga 565 | leafEA _ = error "leafEA"
1375 :    
1376 : leunga 731 and int2real(ty, e) =
1377 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1378 :     in cleanupCode := !cleanupCode @ cleanup;
1379 :     (INTEGER, ty, ea)
1380 : george 545 end
1381 : leunga 731
1382 :     in gencode(su fexp);
1383 :     emits(!cleanupCode)
1384 : george 545 end (*reduceFexp*)
1385 : leunga 731
1386 :     (*========================================================
1387 :     * This section generates 3-address style floating
1388 :     * point code.
1389 :     *========================================================*)
1390 :    
1391 :     and isize 16 = I.I16
1392 :     | isize 32 = I.I32
1393 :     | isize _ = error "isize"
1394 :    
1395 :     and fstore''(fty, ea, d, mem, an) =
1396 :     (floatingPointUsed := true;
1397 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1398 :     src=foperand(fty, d)},
1399 :     an)
1400 :     )
1401 :    
1402 :     and fload''(fty, ea, mem, d, an) =
1403 :     (floatingPointUsed := true;
1404 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1405 :     dst=RealReg d}, an)
1406 :     )
1407 :    
1408 :     and fiload''(ity, ea, d, an) =
1409 :     (floatingPointUsed := true;
1410 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1411 :     )
1412 :    
1413 :     and fexpr''(e as T.FREG(_,f)) =
1414 :     if isFMemReg f then transFexpr e else f
1415 :     | fexpr'' e = transFexpr e
1416 :    
1417 :     and transFexpr e =
1418 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1419 :    
1420 :     (*
1421 :     * Process a floating point operand. Put operand in register
1422 :     * when possible. The operand should match the given fty.
1423 :     *)
1424 :     and foperand(fty, e as T.FREG(fty', f)) =
1425 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1426 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1427 :     foperand(fty, e) (* nop on the x86 *)
1428 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1429 :     (* fold operand when the precison matches *)
1430 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1431 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1432 :    
1433 :     (*
1434 :     * Process a floating point operand.
1435 :     * Try to fold in a memory operand or conversion from an integer.
1436 :     *)
1437 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1438 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1439 :     (REAL, fty, address(ea, mem), [])
1440 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1441 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1442 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1443 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1444 :    
1445 :     (* Generate binary operator. Since the real binary operators
1446 :     * does not take memory as destination, we also ensure this
1447 :     * does not happen.
1448 :     *)
1449 :     and fbinop(targetFty,
1450 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1451 :     (* Put the mem operand in rsrc *)
1452 :     let val _ = floatingPointUsed := true;
1453 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1454 :     | isMemOpnd(T.FLOAD _) = true
1455 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1456 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1457 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1458 :     | isMemOpnd _ = false
1459 :     val (binOp, ibinOp, lsrc, rsrc) =
1460 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1461 :     else (binOp, ibinOp, lsrc, rsrc)
1462 :     val lsrc = foperand(targetFty, lsrc)
1463 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1464 :     fun dstMustBeFreg f =
1465 :     if targetFty <> 64 then
1466 :     let val tmpR = newFreg()
1467 :     val tmp = I.FPR tmpR
1468 :     in mark(f tmp, an);
1469 :     emit(I.FMOVE{fsize=fsize targetFty,
1470 :     src=tmp, dst=RealReg fd})
1471 :     end
1472 :     else mark(f(RealReg fd), an)
1473 :     in case kind of
1474 :     REAL =>
1475 :     dstMustBeFreg(fn dst =>
1476 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1477 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1478 :     | INTEGER =>
1479 :     (dstMustBeFreg(fn dst =>
1480 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1481 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1482 :     emits code
1483 :     )
1484 :     end
1485 : george 545
1486 : leunga 731 and funop(fty, unOp, src, fd, an) =
1487 :     let val src = foperand(fty, src)
1488 :     in mark(I.FUNOP{fsize=fsize fty,
1489 :     unOp=unOp, src=src, dst=RealReg fd},an)
1490 :     end
1491 :    
1492 :     and doFexpr''(fty, e, fd, an) =
1493 :     case e of
1494 : leunga 744 T.FREG(_,fs) => if C.sameColor(fs,fd) then ()
1495 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1496 :     (* Stupid x86 does everything as 80-bits internally. *)
1497 :    
1498 :     (* Binary operators *)
1499 :     | T.FADD(_, a, b) => fbinop(fty,
1500 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1501 :     a, b, fd, an)
1502 :     | T.FSUB(_, a, b) => fbinop(fty,
1503 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1504 :     a, b, fd, an)
1505 :     | T.FMUL(_, a, b) => fbinop(fty,
1506 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1507 :     a, b, fd, an)
1508 :     | T.FDIV(_, a, b) => fbinop(fty,
1509 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1510 :     a, b, fd, an)
1511 :    
1512 :     (* Unary operators *)
1513 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1514 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1515 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1516 :    
1517 :     (* Load *)
1518 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1519 :    
1520 :     (* Type conversions *)
1521 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1522 :     | T.CVTI2F(_, ty, e) =>
1523 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1524 :     in fiload''(ty, ea, fd, an);
1525 :     emits cleanup
1526 :     end
1527 :    
1528 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1529 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1530 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1531 :     | T.FEXT fexp =>
1532 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1533 :     | _ => error("doFexpr''")
1534 :    
1535 :     (*========================================================
1536 :     * Tie the two styles of fp code generation together
1537 :     *========================================================*)
1538 :     and fstore(fty, ea, d, mem, an) =
1539 :     if enableFastFPMode andalso !fast_floating_point
1540 :     then fstore''(fty, ea, d, mem, an)
1541 :     else fstore'(fty, ea, d, mem, an)
1542 :     and fload(fty, ea, d, mem, an) =
1543 :     if enableFastFPMode andalso !fast_floating_point
1544 :     then fload''(fty, ea, d, mem, an)
1545 :     else fload'(fty, ea, d, mem, an)
1546 :     and fexpr e =
1547 :     if enableFastFPMode andalso !fast_floating_point
1548 :     then fexpr'' e else fexpr' e
1549 :     and doFexpr(fty, e, fd, an) =
1550 :     if enableFastFPMode andalso !fast_floating_point
1551 :     then doFexpr''(fty, e, fd, an)
1552 :     else doFexpr'(fty, e, fd, an)
1553 :    
1554 : george 545 (* generate code for a statement *)
1555 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1556 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1557 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1558 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1559 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1560 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1561 :     | stmt(T.CALL{funct, targets, defs, uses, region, ...}, an) =
1562 : leunga 591 call(funct,targets,defs,uses,region,an)
1563 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1564 :     | stmt(T.STORE(8, ea, d, mem), an) = store8(ea, d, mem, an)
1565 :     | stmt(T.STORE(16, ea, d, mem), an) = store16(ea, d, mem, an)
1566 :     | stmt(T.STORE(32, ea, d, mem), an) = store32(ea, d, mem, an)
1567 :     | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1568 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1569 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1570 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1571 : george 555 | stmt(T.EXT s, an) =
1572 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1573 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1574 :    
1575 :     and doStmt s = stmt(s, [])
1576 :     and doStmts ss = app doStmt ss
1577 :    
1578 :     and beginCluster' _ =
1579 :     ((* Must be cleared by the client.
1580 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1581 :     *)
1582 : leunga 731 floatingPointUsed := false;
1583 :     trapLabel := NONE;
1584 :     beginCluster 0
1585 :     )
1586 : george 545 and endCluster' a =
1587 : monnier 247 (case !trapLabel
1588 : monnier 411 of NONE => ()
1589 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1590 : monnier 411 (*esac*);
1591 : leunga 731 (* If floating point has been used allocate an extra
1592 :     * register just in case we didn't use any explicit register
1593 :     *)
1594 :     if !floatingPointUsed then (newFreg(); ())
1595 :     else ();
1596 : george 545 endCluster(a)
1597 :     )
1598 :    
1599 :     and reducer() =
1600 :     T.REDUCER{reduceRexp = expr,
1601 :     reduceFexp = fexpr,
1602 :     reduceCCexp = ccExpr,
1603 :     reduceStm = stmt,
1604 :     operand = operand,
1605 :     reduceOperand = reduceOpnd,
1606 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1607 :     emit = mark,
1608 :     instrStream = instrStream,
1609 :     mltreeStream = self()
1610 :     }
1611 :    
1612 :     and self() =
1613 :     S.STREAM
1614 :     { beginCluster= beginCluster',
1615 :     endCluster = endCluster',
1616 :     emit = doStmt,
1617 :     pseudoOp = pseudoOp,
1618 :     defineLabel = defineLabel,
1619 :     entryLabel = entryLabel,
1620 :     comment = comment,
1621 :     annotation = annotation,
1622 : leunga 744 exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1623 : george 545 }
1624 :    
1625 :     in self()
1626 : monnier 247 end
1627 :    
1628 : george 545 end (* functor *)
1629 :    
1630 :     end (* local *)

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