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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 : leunga 797 structure MLTreeUtils : MLTREE_UTILS
43 :     where T = X86Instr.T
44 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
45 : leunga 775 where I = X86Instr
46 : george 545 datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
47 :     val arch : arch ref
48 : leunga 593 val cvti2f :
49 :     (* source operand, guaranteed to be non-memory! *)
50 : leunga 775 {ty: X86Instr.T.ty, src: X86Instr.operand} ->
51 : leunga 593 {instrs : X86Instr.instruction list,(* the instructions *)
52 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
53 :     cleanup: X86Instr.instruction list (* cleanup code *)
54 :     }
55 : leunga 731 (* When the following flag is set, we allocate floating point registers
56 :     * directly on the floating point stack
57 :     *)
58 :     val fast_floating_point : bool ref
59 : george 545 ) : sig include MLTREECOMP
60 :     val rewriteMemReg : bool
61 :     end =
62 : monnier 247 struct
63 : leunga 775 structure I = X86Instr
64 :     structure T = I.T
65 : monnier 429 structure S = T.Stream
66 : george 545 structure C = I.C
67 :     structure Shuffle = Shuffle(I)
68 : monnier 247 structure W32 = Word32
69 : george 545 structure LE = I.LabelExp
70 :     structure A = MLRiscAnnotations
71 : monnier 247
72 : leunga 744 type instrStream = (I.instruction,C.cellset) T.stream
73 :     type mltreeStream = (T.stm,T.mlrisc list) T.stream
74 : leunga 565
75 :     datatype kind = REAL | INTEGER
76 : george 545
77 :     structure Gen = MLTreeGen
78 :     (structure T = T
79 :     val intTy = 32
80 :     val naturalWidths = [32]
81 :     datatype rep = SE | ZE | NEITHER
82 :     val rep = NEITHER
83 :     )
84 :    
85 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
86 : monnier 247
87 : george 545 (* Should we perform automatic MemReg translation?
88 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
89 :     *)
90 :     val rewriteMemReg = rewriteMemReg
91 : leunga 731
92 :     (* The following hardcoded *)
93 : leunga 744 fun isMemReg r = rewriteMemReg andalso
94 :     let val r = C.registerNum r
95 :     in r >= 8 andalso r < 32
96 :     end
97 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
98 : leunga 744 then let val r = C.registerNum r
99 :     in r >= 8 andalso r < 32 end
100 : leunga 731 else true
101 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
102 :     let val r = C.registerNum r
103 :     in r >= 8 andalso r < 32 end
104 :     )
105 : monnier 247
106 : george 555 val ST0 = C.ST 0
107 :     val ST7 = C.ST 7
108 : leunga 797 val one = T.I.int_1
109 : george 555
110 : leunga 797 val opcodes8 = {INC=I.INCB,DEC=I.DECB,ADD=I.ADDB,SUB=I.SUBB,
111 :     NOT=I.NOTB,NEG=I.NEGB,
112 :     SHL=I.SHLB,SHR=I.SHRB,SAR=I.SARB,
113 :     OR=I.ORB,AND=I.ANDB,XOR=I.XORB}
114 :     val opcodes16 = {INC=I.INCW,DEC=I.DECW,ADD=I.ADDW,SUB=I.SUBW,
115 :     NOT=I.NOTW,NEG=I.NEGW,
116 :     SHL=I.SHLW,SHR=I.SHRW,SAR=I.SARW,
117 :     OR=I.ORW,AND=I.ANDW,XOR=I.XORW}
118 :     val opcodes32 = {INC=I.INCL,DEC=I.DECL,ADD=I.ADDL,SUB=I.SUBL,
119 :     NOT=I.NOTL,NEG=I.NEGL,
120 :     SHL=I.SHLL,SHR=I.SHRL,SAR=I.SARL,
121 :     OR=I.ORL,AND=I.ANDL,XOR=I.XORL}
122 :    
123 : george 545 (*
124 :     * The code generator
125 :     *)
126 : monnier 411 fun selectInstructions
127 : george 545 (instrStream as
128 :     S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,
129 : leunga 744 beginCluster,endCluster,exitBlock,comment,...}) =
130 : george 545 let exception EA
131 : monnier 411
132 : george 545 (* label where a trap is generated -- one per cluster *)
133 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
134 : monnier 247
135 : leunga 731 (* flag floating point generation *)
136 :     val floatingPointUsed = ref false
137 :    
138 : george 545 (* effective address of an integer register *)
139 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
140 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
141 : monnier 411
142 : george 545 (* Add an overflow trap *)
143 :     fun trap() =
144 :     let val jmp =
145 :     case !trapLabel of
146 :     NONE => let val label = Label.newLabel "trap"
147 :     val jmp = I.JCC{cond=I.O,
148 : leunga 775 opnd=I.ImmedLabel(T.LABEL label)}
149 : george 545 in trapLabel := SOME(jmp, label); jmp end
150 :     | SOME(jmp, _) => jmp
151 :     in emit jmp end
152 : monnier 411
153 : george 545 val newReg = C.newReg
154 :     val newFreg = C.newFreg
155 : monnier 247
156 : leunga 731 fun fsize 32 = I.FP32
157 :     | fsize 64 = I.FP64
158 :     | fsize 80 = I.FP80
159 :     | fsize _ = error "fsize"
160 :    
161 : george 545 (* mark an expression with a list of annotations *)
162 :     fun mark'(i,[]) = i
163 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
164 : monnier 247
165 : george 545 (* annotate an expression and emit it *)
166 :     fun mark(i,an) = emit(mark'(i,an))
167 : monnier 247
168 : leunga 731 val emits = app emit
169 :    
170 : george 545 (* emit parallel copies for integers
171 :     * Translates parallel copies that involve memregs into
172 :     * individual copies.
173 :     *)
174 :     fun copy([], [], an) = ()
175 :     | copy(dst, src, an) =
176 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
177 : leunga 744 if C.sameColor(rd,rs) then [] else
178 : george 545 let val tmpR = I.Direct(newReg())
179 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
180 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
181 :     end
182 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
183 : leunga 744 if C.sameColor(rd,rs) then []
184 : george 545 else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
185 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
186 :     in
187 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
188 : leunga 744 {tmp=SOME(I.Direct(newReg())),
189 : george 545 dst=dst, src=src})
190 :     end
191 :    
192 :     (* conversions *)
193 :     val itow = Word.fromInt
194 :     val wtoi = Word.toInt
195 : george 761 fun toInt32 i = T.I.toInt32(32, i)
196 : george 545 val w32toi32 = Word32.toLargeIntX
197 :     val i32tow32 = Word32.fromLargeInt
198 : monnier 247
199 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
200 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
201 : monnier 247
202 : george 545 (* some useful registers *)
203 :     val eax = I.Direct(C.eax)
204 :     val ecx = I.Direct(C.ecx)
205 :     val edx = I.Direct(C.edx)
206 : monnier 247
207 : leunga 775 fun immedLabel lab = I.ImmedLabel(T.LABEL lab)
208 : george 545
209 :     (* Is the expression zero? *)
210 : george 761 fun isZero(T.LI z) = T.I.isZero z
211 : george 545 | isZero(T.MARK(e,a)) = isZero e
212 :     | isZero _ = false
213 :     (* Does the expression set the zero bit?
214 :     * WARNING: we assume these things are not optimized out!
215 :     *)
216 :     fun setZeroBit(T.ANDB _) = true
217 :     | setZeroBit(T.ORB _) = true
218 :     | setZeroBit(T.XORB _) = true
219 :     | setZeroBit(T.SRA _) = true
220 :     | setZeroBit(T.SRL _) = true
221 :     | setZeroBit(T.SLL _) = true
222 : leunga 695 | setZeroBit(T.SUB _) = true
223 :     | setZeroBit(T.ADDT _) = true
224 :     | setZeroBit(T.SUBT _) = true
225 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
226 :     | setZeroBit _ = false
227 : monnier 247
228 : leunga 695 fun setZeroBit2(T.ANDB _) = true
229 :     | setZeroBit2(T.ORB _) = true
230 :     | setZeroBit2(T.XORB _) = true
231 :     | setZeroBit2(T.SRA _) = true
232 :     | setZeroBit2(T.SRL _) = true
233 :     | setZeroBit2(T.SLL _) = true
234 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
235 :     | setZeroBit2(T.SUB _) = true
236 :     | setZeroBit2(T.ADDT _) = true
237 :     | setZeroBit2(T.SUBT _) = true
238 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
239 :     | setZeroBit2 _ = false
240 :    
241 : leunga 731 (* emit parallel copies for floating point
242 :     * Normal version.
243 :     *)
244 :     fun fcopy'(fty, [], [], _) = ()
245 :     | fcopy'(fty, dst as [_], src as [_], an) =
246 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
247 : leunga 731 | fcopy'(fty, dst, src, an) =
248 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
249 : monnier 247
250 : leunga 731 (* emit parallel copies for floating point.
251 :     * Fast version.
252 :     * Translates parallel copies that involve memregs into
253 :     * individual copies.
254 :     *)
255 :    
256 :     fun fcopy''(fty, [], [], _) = ()
257 :     | fcopy''(fty, dst, src, an) =
258 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
259 :     let val fsize = fsize fty
260 :     fun mvInstr{dst, src} = [I.FMOVE{fsize=fsize, src=src, dst=dst}]
261 :     in
262 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
263 : leunga 744 {tmp=case dst of
264 : leunga 731 [_] => NONE
265 :     | _ => SOME(I.FPR(newReg())),
266 :     dst=dst, src=src})
267 :     end
268 :     else
269 :     mark(I.FCOPY{dst=dst,src=src,tmp=
270 :     case dst of
271 :     [_] => NONE
272 :     | _ => SOME(I.FPR(newFreg()))}, an)
273 :    
274 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
275 :     then fcopy'' x else fcopy' x
276 :    
277 : george 545 (* Translates MLTREE condition code to x86 condition code *)
278 :     fun cond T.LT = I.LT | cond T.LTU = I.B
279 :     | cond T.LE = I.LE | cond T.LEU = I.BE
280 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
281 :     | cond T.GE = I.GE | cond T.GEU = I.AE
282 :     | cond T.GT = I.GT | cond T.GTU = I.A
283 : monnier 247
284 : george 545 (* Move and annotate *)
285 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
286 : leunga 744 if C.sameColor(s,d) then ()
287 : george 545 else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
288 :     | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
289 : monnier 247
290 : george 545 (* Move only! *)
291 :     fun move(src, dst) = move'(src, dst, [])
292 : monnier 247
293 : george 545 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
294 : monnier 247
295 : george 545 val readonly = I.Region.readonly
296 : monnier 247
297 : george 545 (*
298 : george 761 * Compute an effective address.
299 : george 545 *)
300 : george 761 fun address(ea, mem) = let
301 : george 545 (* Keep building a bigger and bigger effective address expressions
302 :     * The input is a list of trees
303 :     * b -- base
304 :     * i -- index
305 :     * s -- scale
306 :     * d -- immed displacement
307 :     *)
308 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
309 :     | doEA(t::trees, b, i, s, d) =
310 :     (case t of
311 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
312 : leunga 775 | T.CONST _ => doEALabel(trees, t, b, i, s, d)
313 :     | T.LABEL _ => doEALabel(trees, t, b, i, s, d)
314 :     | T.LABEXP le => doEALabel(trees, le, b, i, s, d)
315 : george 545 | T.ADD(32, t1, t2 as T.REG(_,r)) =>
316 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
317 :     else doEA(t1::t2::trees, b, i, s, d)
318 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
319 :     | T.SUB(32, t1, T.LI n) =>
320 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
321 :     | T.SLL(32, t1, T.LI n) => let
322 :     val n = T.I.toInt(32, n)
323 :     in
324 :     case n
325 :     of 0 => displace(trees, t1, b, i, s, d)
326 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
327 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
328 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
329 :     | _ => displace(trees, t, b, i, s, d)
330 :     end
331 : george 545 | t => displace(trees, t, b, i, s, d)
332 :     )
333 : monnier 247
334 : george 545 (* Add an immed constant *)
335 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
336 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
337 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
338 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
339 : leunga 775 doEA(trees, b, i, s,
340 :     I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, n)))))
341 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
342 : monnier 247
343 : george 545 (* Add a label expression *)
344 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
345 :     doEA(trees, b, i, s, I.ImmedLabel le)
346 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
347 :     doEA(trees, b, i, s,
348 : leunga 775 I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, m))))
349 : george 545 handle Overflow => error "doEALabel: constant too large")
350 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
351 : leunga 775 doEA(trees, b, i, s, I.ImmedLabel(T.ADD(32,le,le')))
352 : george 545 | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
353 : monnier 247
354 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
355 :     | makeAddressingMode(SOME base, NONE, _, disp) =
356 :     I.Displace{base=base, disp=disp, mem=mem}
357 :     | makeAddressingMode(base, SOME index, scale, disp) =
358 : george 761 I.Indexed{base=base, index=index, scale=scale,
359 : george 545 disp=disp, mem=mem}
360 : monnier 247
361 : george 545 (* generate code for tree and ensure that it is not in %esp *)
362 :     and exprNotEsp tree =
363 :     let val r = expr tree
364 : leunga 744 in if C.sameColor(r, C.esp) then
365 : george 545 let val tmp = newReg()
366 :     in move(I.Direct r, I.Direct tmp); tmp end
367 :     else r
368 :     end
369 : monnier 247
370 : george 545 (* Add a base register *)
371 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
372 :     doEA(trees, SOME(expr t), i, s, d)
373 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
374 :     (* make t the index, but make sure that it is not %esp! *)
375 :     let val i = expr t
376 : leunga 744 in if C.sameColor(i, C.esp) then
377 : george 545 (* swap base and index *)
378 : leunga 744 if C.sameColor(base, C.esp) then
379 : george 545 doEA(trees, SOME i, b, 0, d)
380 :     else (* base and index = %esp! *)
381 :     let val index = newReg()
382 :     in move(I.Direct i, I.Direct index);
383 :     doEA(trees, b, SOME index, 0, d)
384 :     end
385 :     else
386 :     doEA(trees, b, SOME i, 0, d)
387 :     end
388 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
389 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
390 :     in doEA(trees, SOME b, i, s, d) end
391 : monnier 247
392 : george 545 (* Add an indexed register *)
393 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
394 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
395 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
396 :     doEA(trees, SOME(expr t0), i, s, d)
397 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
398 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
399 :     in doEA(trees, SOME b, i, s, d) end
400 :    
401 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
402 :     I.Immed _ => raise EA
403 :     | I.ImmedLabel le => I.LabelEA le
404 :     | ea => ea
405 :     end (* address *)
406 : monnier 247
407 : george 545 (* reduce an expression into an operand *)
408 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
409 : leunga 775 | operand(x as (T.CONST _ | T.LABEL _)) = I.ImmedLabel x
410 :     | operand(T.LABEXP le) = I.ImmedLabel le
411 : george 545 | operand(T.REG(_,r)) = IntReg r
412 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
413 :     | operand(t) = I.Direct(expr t)
414 : monnier 247
415 : george 545 and moveToReg(opnd) =
416 :     let val dst = I.Direct(newReg())
417 :     in move(opnd, dst); dst
418 :     end
419 : monnier 247
420 : george 545 and reduceOpnd(I.Direct r) = r
421 :     | reduceOpnd opnd =
422 :     let val dst = newReg()
423 :     in move(opnd, I.Direct dst); dst
424 :     end
425 : monnier 247
426 : george 545 (* ensure that the operand is either an immed or register *)
427 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
428 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
429 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
430 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
431 :     | immedOrReg opnd = opnd
432 : monnier 247
433 : george 545 and isImmediate(I.Immed _) = true
434 :     | isImmediate(I.ImmedLabel _) = true
435 :     | isImmediate _ = false
436 : monnier 247
437 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
438 :    
439 :     and isMemOpnd opnd =
440 :     (case opnd of
441 :     I.Displace _ => true
442 :     | I.Indexed _ => true
443 :     | I.MemReg _ => true
444 :     | I.LabelEA _ => true
445 : george 555 | I.FDirect f => true
446 : george 545 | _ => false
447 :     )
448 :    
449 :     (*
450 :     * Compute an integer expression and put the result in
451 :     * the destination register rd.
452 :     *)
453 :     and doExpr(exp, rd : I.C.cell, an) =
454 :     let val rdOpnd = IntReg rd
455 : monnier 247
456 : leunga 744 fun equalRd(I.Direct r) = C.sameColor(r, rd)
457 :     | equalRd(I.MemReg r) = C.sameColor(r, rd)
458 : george 545 | equalRd _ = false
459 : monnier 247
460 : george 545 (* Emit a binary operator. If the destination is
461 :     * a memReg, do something smarter.
462 :     *)
463 :     fun genBinary(binOp, opnd1, opnd2) =
464 :     if isMemReg rd andalso
465 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
466 :     equalRd(opnd2)
467 :     then
468 :     let val tmpR = newReg()
469 :     val tmp = I.Direct tmpR
470 :     in move(opnd1, tmp);
471 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
472 :     move(tmp, rdOpnd)
473 :     end
474 :     else
475 :     (move(opnd1, rdOpnd);
476 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
477 :     )
478 : monnier 247
479 : george 545 (* Generate a binary operator; it may commute *)
480 :     fun binaryComm(binOp, e1, e2) =
481 :     let val (opnd1, opnd2) =
482 :     case (operand e1, operand e2) of
483 :     (x as I.Immed _, y) => (y, x)
484 :     | (x as I.ImmedLabel _, y) => (y, x)
485 :     | (x, y as I.Direct _) => (y, x)
486 :     | (x, y) => (x, y)
487 :     in genBinary(binOp, opnd1, opnd2)
488 :     end
489 :    
490 :     (* Generate a binary operator; non-commutative *)
491 :     fun binary(binOp, e1, e2) =
492 :     genBinary(binOp, operand e1, operand e2)
493 :    
494 :     (* Generate a unary operator *)
495 :     fun unary(unOp, e) =
496 :     let val opnd = operand e
497 :     in if isMemReg rd andalso isMemOpnd opnd then
498 :     let val tmp = I.Direct(newReg())
499 :     in move(opnd, tmp); move(tmp, rdOpnd)
500 :     end
501 :     else move(opnd, rdOpnd);
502 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
503 :     end
504 :    
505 :     (* Generate shifts; the shift
506 :     * amount must be a constant or in %ecx *)
507 :     fun shift(opcode, e1, e2) =
508 :     let val (opnd1, opnd2) = (operand e1, operand e2)
509 :     in case opnd2 of
510 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
511 :     | _ =>
512 :     if equalRd(opnd2) then
513 :     let val tmpR = newReg()
514 :     val tmp = I.Direct tmpR
515 :     in move(opnd1, tmp);
516 :     move(opnd2, ecx);
517 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
518 :     move(tmp, rdOpnd)
519 :     end
520 :     else
521 :     (move(opnd1, rdOpnd);
522 :     move(opnd2, ecx);
523 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
524 :     )
525 :     end
526 :    
527 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
528 :     fun divrem(signed, overflow, e1, e2, resultReg) =
529 :     let val (opnd1, opnd2) = (operand e1, operand e2)
530 :     val _ = move(opnd1, eax)
531 : leunga 606 val oper = if signed then (emit(I.CDQ); I.IDIVL)
532 :     else (zero edx; I.DIVL)
533 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
534 :     move(resultReg, rdOpnd);
535 :     if overflow then trap() else ()
536 :     end
537 :    
538 :     (* Optimize the special case for division *)
539 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
540 :     val n = toInt32 n'
541 :     val w = T.I.toWord32(32, n')
542 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
543 : george 545 fun log2 n = (* n must be > 0!!! *)
544 :     let fun loop(0w1,pow) = pow
545 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
546 : george 545 in loop(n,0) end
547 :     in if n > 1 andalso isPowerOf2 w then
548 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
549 : george 545 in if signed then
550 :     (* signed; simulate round towards zero *)
551 :     let val label = Label.newLabel ""
552 :     val reg1 = expr e1
553 :     val opnd1 = I.Direct reg1
554 :     in if setZeroBit e1 then ()
555 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
556 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
557 :     emit(if n = 2 then
558 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
559 :     else
560 :     I.BINARY{binOp=I.ADDL,
561 : george 761 src=I.Immed(n - 1),
562 : george 545 dst=opnd1});
563 :     defineLabel label;
564 :     shift(I.SARL, T.REG(32, reg1), pow)
565 :     end
566 :     else (* unsigned *)
567 :     shift(I.SHRL, e1, pow)
568 :     end
569 :     else
570 :     (* note the only way we can overflow is if
571 :     * n = 0 or n = -1
572 :     *)
573 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
574 :     e1, e2, eax)
575 :     end
576 :     | divide(signed, overflow, e1, e2) =
577 :     divrem(signed, overflow, e1, e2, eax)
578 : monnier 247
579 : george 545 fun rem(signed, overflow, e1, e2) =
580 :     divrem(signed, overflow, e1, e2, edx)
581 :    
582 :     (* unsigned integer multiplication *)
583 :     fun uMultiply(e1, e2) =
584 :     (* note e2 can never be (I.Direct edx) *)
585 :     (move(operand e1, eax);
586 : leunga 606 mark(I.MULTDIV{multDivOp=I.MULL,
587 : george 545 src=regOrMem(operand e2)},an);
588 :     move(eax, rdOpnd)
589 :     )
590 :    
591 :     (* signed integer multiplication:
592 :     * The only forms that are allowed that also sets the
593 :     * OF and CF flags are:
594 :     *
595 :     * imul r32, r32/m32, imm8
596 :     * imul r32, imm8
597 :     * imul r32, imm32
598 :     *)
599 :     fun multiply(e1, e2) =
600 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _, dstR, dst) =
601 :     (move(i1, dst);
602 :     mark(I.MUL3{dst=dstR, src1=i2, src2=NONE},an))
603 :     | doit(rm, i2 as I.Immed _, dstR, dst) =
604 :     doit(i2, rm, dstR, dst)
605 :     | doit(imm as I.Immed(i), rm, dstR, dst) =
606 :     mark(I.MUL3{dst=dstR, src1=rm, src2=SOME i},an)
607 :     | doit(r1 as I.Direct _, r2 as I.Direct _, dstR, dst) =
608 :     (move(r1, dst);
609 :     mark(I.MUL3{dst=dstR, src1=r2, src2=NONE},an))
610 :     | doit(r1 as I.Direct _, rm, dstR, dst) =
611 :     (move(r1, dst);
612 :     mark(I.MUL3{dst=dstR, src1=rm, src2=NONE},an))
613 :     | doit(rm, r as I.Direct _, dstR, dst) =
614 :     doit(r, rm, dstR, dst)
615 :     | doit(rm1, rm2, dstR, dst) =
616 :     if equalRd rm2 then
617 :     let val tmpR = newReg()
618 :     val tmp = I.Direct tmpR
619 :     in move(rm1, tmp);
620 :     mark(I.MUL3{dst=tmpR, src1=rm2, src2=NONE},an);
621 :     move(tmp, dst)
622 :     end
623 :     else
624 :     (move(rm1, dst);
625 :     mark(I.MUL3{dst=dstR, src1=rm2, src2=NONE},an)
626 :     )
627 :     val (opnd1, opnd2) = (operand e1, operand e2)
628 :     in if isMemReg rd then (* destination must be a real reg *)
629 :     let val tmpR = newReg()
630 :     val tmp = I.Direct tmpR
631 :     in doit(opnd1, opnd2, tmpR, tmp);
632 :     move(tmp, rdOpnd)
633 :     end
634 :     else
635 :     doit(opnd1, opnd2, rd, rdOpnd)
636 :     end
637 : monnier 247
638 : george 545 (* Makes sure the destination must be a register *)
639 :     fun dstMustBeReg f =
640 :     if isMemReg rd then
641 :     let val tmpR = newReg()
642 :     val tmp = I.Direct(tmpR)
643 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
644 :     else f(rd, rdOpnd)
645 : monnier 247
646 : george 545 (* Emit a load instruction; makes sure that the destination
647 :     * is a register
648 :     *)
649 :     fun genLoad(mvOp, ea, mem) =
650 :     dstMustBeReg(fn (_, dst) =>
651 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
652 :    
653 :     (* Generate a zero extended loads *)
654 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
655 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
656 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
657 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
658 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
659 :    
660 :     (* Generate a sign extended loads *)
661 :    
662 :     (* Generate setcc instruction:
663 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
664 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
665 :     * Note that we have to use eax as the destination of the
666 :     * setcc because it only works on the registers
667 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
668 :     * are inaccessible in 32 bit mode.
669 : george 545 *)
670 :     fun setcc(ty, cc, t1, t2, yes, no) =
671 : leunga 583 let val (cc, yes, no) =
672 :     if yes > no then (cc, yes, no)
673 :     else (T.Basis.negateCond cc, no, yes)
674 : george 545 in (* Clear the destination first.
675 :     * This this because stupid SETcc
676 :     * only writes to the low order
677 :     * byte. That's Intel architecture, folks.
678 :     *)
679 : leunga 695 case (yes, no, cc) of
680 :     (1, 0, T.LT) =>
681 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
682 :     in move(tmp, rdOpnd);
683 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
684 :     end
685 :     | (1, 0, T.GT) =>
686 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
687 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
688 :     move(tmp, rdOpnd);
689 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
690 :     end
691 :     | (1, 0, _) => (* normal case *)
692 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
693 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
694 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
695 : leunga 583 move(eax, rdOpnd)
696 :     end
697 : leunga 695 | (C1, C2, _) =>
698 : george 545 (* general case;
699 : leunga 583 * from the Intel optimization guide p3-5
700 :     *)
701 : leunga 695 let val _ = zero eax;
702 :     val cc = cmp(true, ty, cc, t1, t2, [])
703 : leunga 583 in case C1-C2 of
704 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
705 :     let val (base,scale) =
706 :     case D of
707 :     1 => (NONE, 0)
708 :     | 2 => (NONE, 1)
709 :     | 3 => (SOME C.eax, 1)
710 :     | 4 => (NONE, 2)
711 :     | 5 => (SOME C.eax, 2)
712 :     | 8 => (NONE, 3)
713 :     | 9 => (SOME C.eax, 3)
714 :     val addr = I.Indexed{base=base,
715 :     index=C.eax,
716 :     scale=scale,
717 :     disp=I.Immed C2,
718 : george 545 mem=readonly}
719 : leunga 583 val tmpR = newReg()
720 :     val tmp = I.Direct tmpR
721 :     in emit(I.SET{cond=cond cc, opnd=eax});
722 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
723 :     move(tmp, rdOpnd)
724 :     end
725 :     | D =>
726 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
727 :     opnd=eax});
728 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
729 :     emit(I.BINARY{binOp=I.ANDL,
730 :     src=I.Immed D, dst=eax});
731 :     if C2 = 0 then
732 :     move(eax, rdOpnd)
733 :     else
734 :     let val tmpR = newReg()
735 :     val tmp = I.Direct tmpR
736 :     in mark(I.LEA{addr=
737 :     I.Displace{
738 :     base=C.eax,
739 :     disp=I.Immed C2,
740 :     mem=readonly},
741 :     r32=tmpR}, an);
742 :     move(tmp, rdOpnd)
743 :     end
744 :     )
745 :     end
746 : george 545 end (* setcc *)
747 :    
748 :     (* Generate cmovcc instruction.
749 :     * on Pentium Pro and Pentium II only
750 :     *)
751 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
752 :     let fun genCmov(dstR, _) =
753 :     let val _ = doExpr(no, dstR, []) (* false branch *)
754 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
755 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
756 :     end
757 :     in dstMustBeReg genCmov
758 :     end
759 :    
760 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
761 : monnier 247
762 : leunga 606 (* Add n to rd *)
763 :     fun addN n =
764 :     let val n = operand n
765 :     val src = if isMemReg rd then immedOrReg n else n
766 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
767 :    
768 : george 545 (* Generate addition *)
769 :     fun addition(e1, e2) =
770 : leunga 606 case e1 of
771 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e2
772 :     else addition1(e1,e2)
773 : leunga 606 | _ => addition1(e1,e2)
774 :     and addition1(e1, e2) =
775 :     case e2 of
776 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e1
777 :     else addition2(e1,e2)
778 : leunga 606 | _ => addition2(e1,e2)
779 :     and addition2(e1,e2) =
780 : george 545 (dstMustBeReg(fn (dstR, _) =>
781 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
782 :     handle EA => binaryComm(I.ADDL, e1, e2))
783 : monnier 247
784 :    
785 : george 545 in case exp of
786 :     T.REG(_,rs) =>
787 :     if isMemReg rs andalso isMemReg rd then
788 :     let val tmp = I.Direct(newReg())
789 : leunga 731 in move'(I.MemReg rs, tmp, an);
790 : george 545 move'(tmp, rdOpnd, [])
791 :     end
792 :     else move'(IntReg rs, rdOpnd, an)
793 : george 761 | T.LI z => let
794 :     val n = toInt32 z
795 :     in
796 :     if n=0 then
797 :     (* As per Fermin's request, special optimization for rd := 0.
798 :     * Currently we don't bother with the size.
799 :     *)
800 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
801 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
802 :     else
803 :     move'(I.Immed(n), rdOpnd, an)
804 :     end
805 : leunga 775 | (T.CONST _ | T.LABEL _) =>
806 :     move'(I.ImmedLabel exp, rdOpnd, an)
807 :     | T.LABEXP le => move'(I.ImmedLabel le, rdOpnd, an)
808 : monnier 247
809 : george 545 (* 32-bit addition *)
810 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
811 :     val n = toInt32 n
812 :     in
813 :     case n
814 :     of 1 => unary(I.INCL, e1)
815 :     | ~1 => unary(I.DECL, e1)
816 :     | _ => addition(e1, e2)
817 :     end
818 :     | T.ADD(32, e1 as T.LI n, e2) => let
819 :     val n = toInt32 n
820 :     in
821 :     case n
822 :     of 1 => unary(I.INCL, e2)
823 :     | ~1 => unary(I.DECL, e2)
824 :     | _ => addition(e1, e2)
825 :     end
826 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
827 : monnier 247
828 : leunga 695 (* 32-bit addition but set the flag!
829 :     * This is a stupid hack for now.
830 :     *)
831 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
832 :     val n = T.I.toInt(32, n)
833 :     in
834 :     if n=1 then unary(I.INCL, e)
835 :     else if n = ~1 then unary(I.DECL, e)
836 :     else binaryComm(I.ADDL, e, e1)
837 :     end
838 :     | T.ADD(0, e1 as T.LI n, e) => let
839 :     val n = T.I.toInt(32, n)
840 :     in
841 :     if n=1 then unary(I.INCL, e)
842 :     else if n = ~1 then unary(I.DECL, e)
843 :     else binaryComm(I.ADDL, e1, e)
844 :     end
845 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
846 :    
847 : george 545 (* 32-bit subtraction *)
848 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
849 :     val n = toInt32 n
850 :     in
851 :     case n
852 :     of 0 => doExpr(e1, rd, an)
853 :     | 1 => unary(I.DECL, e1)
854 :     | ~1 => unary(I.INCL, e1)
855 :     | _ => binary(I.SUBL, e1, e2)
856 :     end
857 :     | T.SUB(32, e1 as T.LI n, e2) =>
858 :     if T.I.isZero n then unary(I.NEGL, e2)
859 :     else binary(I.SUBL, e1, e2)
860 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
861 : monnier 247
862 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
863 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
864 :     | T.REMU(32, x, y) => rem(false, false, x, y)
865 : monnier 247
866 : george 545 | T.MULS(32, x, y) => multiply(x, y)
867 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
868 :     | T.REMS(32, x, y) => rem(true, false, x, y)
869 : monnier 247
870 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
871 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
872 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
873 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
874 :     | T.REMT(32, x, y) => rem(true, true, x, y)
875 : monnier 247
876 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
877 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
878 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
879 :     | T.NOTB(32, x) => unary(I.NOTL, x)
880 : monnier 247
881 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
882 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
883 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
884 : monnier 247
885 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
886 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
887 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
888 : monnier 498
889 : leunga 776 | T.SX(32,8,T.LOAD(8,ea,mem)) => load8s(ea, mem)
890 :     | T.SX(32,16,T.LOAD(16,ea,mem)) => load16s(ea, mem)
891 :     | T.ZX(32,8,T.LOAD(8,ea,mem)) => load8(ea, mem)
892 : leunga 779 | T.ZX(32,16,T.LOAD(16,ea,mem)) => load16(ea, mem)
893 : leunga 776
894 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
895 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
896 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
897 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
898 :     Pentium => unknownExp exp
899 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
900 :     )
901 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
902 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
903 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
904 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
905 : george 555 | T.REXT e =>
906 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
907 : george 545 (* simplify and try again *)
908 :     | exp => unknownExp exp
909 :     end (* doExpr *)
910 : monnier 247
911 : george 545 (* generate an expression and return its result register
912 :     * If rewritePseudo is on, the result is guaranteed to be in a
913 :     * non memReg register
914 :     *)
915 :     and expr(exp as T.REG(_, rd)) =
916 :     if isMemReg rd then genExpr exp else rd
917 :     | expr exp = genExpr exp
918 : monnier 247
919 : george 545 and genExpr exp =
920 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
921 : monnier 247
922 : george 545 (* Compare an expression with zero.
923 :     * On the x86, TEST is superior to AND for doing the same thing,
924 :     * since it doesn't need to write out the result in a register.
925 :     *)
926 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
927 : george 545 (case ty of
928 : leunga 695 8 => test(I.TESTB, a, b, an)
929 :     | 16 => test(I.TESTW, a, b, an)
930 :     | 32 => test(I.TESTL, a, b, an)
931 :     | _ => doExpr(e, newReg(), an);
932 :     cc)
933 :     | cmpWithZero(cc, e, an) =
934 :     let val e =
935 :     case e of (* hack to disable the lea optimization XXX *)
936 :     T.ADD(_, a, b) => T.ADD(0, a, b)
937 :     | e => e
938 :     in doExpr(e, newReg(), an); cc end
939 : monnier 247
940 : george 545 (* Emit a test.
941 :     * The available modes are
942 :     * r/m, r
943 :     * r/m, imm
944 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
945 :     * When anding an operand with a constant
946 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
947 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
948 :     * this works for memory operands too. However, with TESTB, it is
949 :     * not possible to use registers other than
950 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
951 :     * perform register allocation first, and if the operand registers
952 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
953 :     * by TESTB.
954 :     *)
955 : leunga 695 and test(testopcode, a, b, an) =
956 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
957 :     (* translate r, r/m => r/m, r *)
958 :     val (opnd1, opnd2) =
959 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
960 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
961 : george 545 end
962 : monnier 247
963 : george 545 (* generate a condition code expression
964 : leunga 744 * The zero is for setting the condition code!
965 :     * I have no idea why this is used.
966 :     *)
967 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
968 :     if C.sameColor(rd, C.eflags) then
969 :     (cmp(false, ty, cc, t1, t2, an); ())
970 :     else
971 :     error "doCCexpr: cmp"
972 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
973 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
974 :     | doCCexpr(T.CCEXT e, cd, an) =
975 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
976 : george 545 | doCCexpr _ = error "doCCexpr"
977 : monnier 247
978 : george 545 and ccExpr e = error "ccExpr"
979 : monnier 247
980 : george 545 (* generate a comparison and sets the condition code;
981 :     * return the actual cc used. If the flag swapable is true,
982 :     * we can also reorder the operands.
983 :     *)
984 :     and cmp(swapable, ty, cc, t1, t2, an) =
985 : leunga 695 (* == and <> can be always be reordered *)
986 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
987 :     in (* Sometimes the comparison is not necessary because
988 :     * the bits are already set!
989 :     *)
990 :     if isZero t1 andalso setZeroBit2 t2 then
991 :     if swapable then
992 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
993 :     else (* can't reorder the comparison! *)
994 :     genCmp(ty, false, cc, t1, t2, an)
995 :     else if isZero t2 andalso setZeroBit2 t1 then
996 :     cmpWithZero(cc, t1, an)
997 :     else genCmp(ty, swapable, cc, t1, t2, an)
998 :     end
999 : monnier 247
1000 : george 545 (* Give a and b which are the operands to a comparison (or test)
1001 :     * Return the appropriate condition code and operands.
1002 :     * The available modes are:
1003 :     * r/m, imm
1004 :     * r/m, r
1005 :     * r, r/m
1006 :     *)
1007 :     and commuteComparison(cc, swapable, a, b) =
1008 :     let val (opnd1, opnd2) = (operand a, operand b)
1009 :     in (* Try to fold in the operands whenever possible *)
1010 :     case (isImmediate opnd1, isImmediate opnd2) of
1011 :     (true, true) => (cc, moveToReg opnd1, opnd2)
1012 :     | (true, false) =>
1013 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
1014 :     else (cc, moveToReg opnd1, opnd2)
1015 :     | (false, true) => (cc, opnd1, opnd2)
1016 :     | (false, false) =>
1017 :     (case (opnd1, opnd2) of
1018 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1019 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1020 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1021 :     )
1022 :     end
1023 :    
1024 :     (* generate a real comparison; return the real cc used *)
1025 :     and genCmp(ty, swapable, cc, a, b, an) =
1026 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1027 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1028 :     end
1029 : monnier 247
1030 : george 545 (* generate code for jumps *)
1031 : leunga 775 and jmp(lexp as T.LABEL lab, labs, an) =
1032 : george 545 mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1033 : leunga 775 | jmp(T.LABEXP le, labs, an) = mark(I.JMP(I.ImmedLabel le, labs), an)
1034 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1035 : george 545
1036 :     (* convert mlrisc to cellset:
1037 :     *)
1038 :     and cellset mlrisc =
1039 : leunga 744 let val addCCReg = C.CellSet.add
1040 : george 545 fun g([],acc) = acc
1041 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1042 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1043 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1044 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1045 :     | g(_::regs, acc) = g(regs, acc)
1046 :     in g(mlrisc, C.empty) end
1047 :    
1048 :     (* generate code for calls *)
1049 : leunga 796 and call(ea, flow, def, use, mem, cutsTo, an) =
1050 :     mark(I.CALL{opnd=operand ea,defs=cellset(def),uses=cellset(use),
1051 :     cutsTo=cutsTo,mem=mem},an)
1052 : george 545
1053 :     (* generate code for integer stores *)
1054 :     and store8(ea, d, mem, an) =
1055 :     let val src = (* movb has to use %eax as source. Stupid x86! *)
1056 :     case immedOrReg(operand d) of
1057 :     src as I.Direct r =>
1058 : leunga 744 if C.sameColor(r,C.eax)
1059 :     then src else (move(src, eax); eax)
1060 : george 545 | src => src
1061 :     in mark(I.MOVE{mvOp=I.MOVB, src=src, dst=address(ea,mem)},an)
1062 :     end
1063 :     and store16(ea, d, mem, an) = error "store16"
1064 :     and store32(ea, d, mem, an) =
1065 :     move'(immedOrReg(operand d), address(ea, mem), an)
1066 :    
1067 :     (* generate code for branching *)
1068 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1069 :     (* allow reordering of operands *)
1070 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1071 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1072 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1073 :     fbranch(fty, fcc, t1, t2, lab, an)
1074 :     | branch(ccexp, lab, an) =
1075 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1076 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1077 :     )
1078 :    
1079 :     (* generate code for floating point compare and branch *)
1080 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1081 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1082 :     | ignoreOrder (T.FLOAD _) = true
1083 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1084 :     | ignoreOrder _ = false
1085 :    
1086 :     fun compare'() = (* Sethi-Ullman style *)
1087 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1088 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1089 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1090 :     emit(I.FXCH{opnd=C.ST(1)}));
1091 :     emit(I.FUCOMPP);
1092 :     fcc
1093 :     )
1094 :    
1095 :     fun compare''() =
1096 :     (* direct style *)
1097 :     (* Try to make lsrc the memory operand *)
1098 :     let val lsrc = foperand(fty, t1)
1099 :     val rsrc = foperand(fty, t2)
1100 :     val fsize = fsize fty
1101 :     fun cmp(lsrc, rsrc, fcc) =
1102 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1103 :     in case (lsrc, rsrc) of
1104 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1105 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1106 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1107 :     | (lsrc, rsrc) => (* can't be both memory! *)
1108 :     let val ftmpR = newFreg()
1109 :     val ftmp = I.FPR ftmpR
1110 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1111 :     cmp(lsrc, ftmp, fcc)
1112 :     end
1113 :     end
1114 :    
1115 :     fun compare() =
1116 :     if enableFastFPMode andalso !fast_floating_point
1117 :     then compare''() else compare'()
1118 :    
1119 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1120 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1121 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1122 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1123 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1124 :     fun sahf() = emit(I.SAHF)
1125 : leunga 731 fun branch(fcc) =
1126 : george 545 case fcc
1127 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1128 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1129 :     | T.? => (sahf(); j(I.P,lab))
1130 :     | T.<=> => (sahf(); j(I.NP,lab))
1131 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1132 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1133 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1134 :     | T.?< => (testil 0x500; j(I.NE,lab))
1135 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1136 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1137 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1138 :     cmpil 0x4000; j(I.EQ,lab))
1139 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1140 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1141 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1142 : george 545 | _ => error "fbranch"
1143 :     (*esac*)
1144 : leunga 731 val fcc = compare()
1145 :     in emit I.FNSTSW;
1146 :     branch(fcc)
1147 : monnier 411 end
1148 : monnier 247
1149 : leunga 731 (*========================================================
1150 :     * Floating point code generation starts here.
1151 :     * Some generic fp routines first.
1152 :     *========================================================*)
1153 :    
1154 :     (* Can this tree be folded into the src operand of a floating point
1155 :     * operations?
1156 :     *)
1157 :     and foldableFexp(T.FREG _) = true
1158 :     | foldableFexp(T.FLOAD _) = true
1159 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1160 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1161 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1162 :     | foldableFexp _ = false
1163 :    
1164 :     (* Move integer e of size ty into a memory location.
1165 :     * Returns a quadruple:
1166 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1167 :     *)
1168 :     and convertIntToFloat(ty, e) =
1169 :     let val opnd = operand e
1170 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1171 :     then (INTEGER, ty, opnd, [])
1172 :     else
1173 :     let val {instrs, tempMem, cleanup} = cvti2f{ty=ty, src=opnd}
1174 :     in emits instrs;
1175 :     (INTEGER, 32, tempMem, cleanup)
1176 :     end
1177 :     end
1178 :    
1179 :     (*========================================================
1180 :     * Sethi-Ullman based floating point code generation as
1181 :     * implemented by Lal
1182 :     *========================================================*)
1183 :    
1184 : george 545 and fld(32, opnd) = I.FLDS opnd
1185 :     | fld(64, opnd) = I.FLDL opnd
1186 : george 555 | fld(80, opnd) = I.FLDT opnd
1187 : george 545 | fld _ = error "fld"
1188 :    
1189 : leunga 565 and fild(16, opnd) = I.FILD opnd
1190 :     | fild(32, opnd) = I.FILDL opnd
1191 :     | fild(64, opnd) = I.FILDLL opnd
1192 :     | fild _ = error "fild"
1193 :    
1194 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1195 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1196 :    
1197 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1198 :     | fstp(64, opnd) = I.FSTPL opnd
1199 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1200 : george 545 | fstp _ = error "fstp"
1201 :    
1202 :     (* generate code for floating point stores *)
1203 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1204 : george 545 (case d of
1205 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1206 :     | _ => reduceFexp(fty, d, []);
1207 :     mark(fstp(fty, address(ea, mem)), an)
1208 :     )
1209 :    
1210 : leunga 731 (* generate code for floating point loads *)
1211 :     and fload'(fty, ea, mem, fd, an) =
1212 :     let val ea = address(ea, mem)
1213 :     in mark(fld(fty, ea), an);
1214 : leunga 744 if C.sameColor(fd,ST0) then ()
1215 :     else emit(fstp(fty, I.FDirect fd))
1216 : leunga 731 end
1217 :    
1218 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1219 : george 545
1220 :     (* generate floating point expression and put the result in fd *)
1221 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1222 : leunga 744 (if C.sameColor(fs,fd) then ()
1223 : george 545 else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
1224 :     )
1225 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1226 :     fload'(fty, ea, mem, fd, an)
1227 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1228 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1229 : leunga 744 if C.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1230 : leunga 731 )
1231 :     | doFexpr'(fty, e, fd, an) =
1232 : george 545 (reduceFexp(fty, e, []);
1233 : leunga 744 if C.sameColor(fd,ST0) then ()
1234 :     else mark(fstp(fty, I.FDirect fd), an)
1235 : george 545 )
1236 :    
1237 :     (*
1238 :     * Generate floating point expression using Sethi-Ullman's scheme:
1239 :     * This function evaluates a floating point expression,
1240 :     * and put result in %ST(0).
1241 :     *)
1242 :     and reduceFexp(fty, fexp, an) =
1243 : george 555 let val ST = I.ST(C.ST 0)
1244 :     val ST1 = I.ST(C.ST 1)
1245 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1246 : george 545
1247 : leunga 565 datatype su_tree =
1248 :     LEAF of int * T.fexp * ans
1249 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1250 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1251 :     and fbinop = FADD | FSUB | FMUL | FDIV
1252 :     | FIADD | FISUB | FIMUL | FIDIV
1253 :     withtype ans = Annotations.annotations
1254 : monnier 247
1255 : leunga 565 fun label(LEAF(n, _, _)) = n
1256 :     | label(BINARY(n, _, _, _, _, _)) = n
1257 :     | label(UNARY(n, _, _, _, _)) = n
1258 : george 545
1259 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1260 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1261 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1262 : george 545
1263 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1264 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1265 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1266 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1267 :     | su(T.CVTF2F(_, _, t)) = su t
1268 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1269 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1270 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1271 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1272 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1273 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1274 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1275 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1276 :     | su _ = error "su"
1277 :    
1278 :     (* Try to fold the the memory operand or integer conversion *)
1279 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1280 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1281 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1282 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1283 :     | suFold(T.FMARK(t, a)) =
1284 :     let val (t, integer) = suFold t
1285 :     in (annotate(t, a), integer) end
1286 :     | suFold e = (su e, false)
1287 :    
1288 :     (* Form unary tree *)
1289 :     and suUnary(fty, funary, t) =
1290 :     let val t = su t
1291 :     in UNARY(label t, fty, funary, t, [])
1292 : george 545 end
1293 : leunga 565
1294 :     (* Form binary tree *)
1295 :     and suBinary(fty, binop, ibinop, t1, t2) =
1296 :     let val t1 = su t1
1297 :     val (t2, integer) = suFold t2
1298 :     val n1 = label t1
1299 :     val n2 = label t2
1300 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1301 :     val myOp = if integer then ibinop else binop
1302 :     in BINARY(n, fty, myOp, t1, t2, [])
1303 : george 545 end
1304 : george 555
1305 : leunga 565 (* Try to fold in the operand if possible.
1306 :     * This only applies to commutative operations.
1307 :     *)
1308 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1309 : leunga 731 let val (t1, t2) = if foldableFexp t2
1310 :     then (t1, t2) else (t2, t1)
1311 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1312 :    
1313 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1314 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1315 :     t1 = t2 andalso C.sameColor(f1,f2)
1316 : leunga 565 | sameTree _ = false
1317 :    
1318 :     (* Traverse tree and generate code *)
1319 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1320 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1321 :     let val _ = gencode x
1322 :     val (_, fty, src) = leafEA y
1323 :     fun gen(code) = mark(code, a1 @ a2)
1324 :     fun binary(oper32, oper64) =
1325 :     if sameTree(x, t2) then
1326 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1327 : george 555 else
1328 :     let val oper =
1329 : leunga 565 if isMemOpnd src then
1330 :     case fty of
1331 :     32 => oper32
1332 :     | 64 => oper64
1333 :     | _ => error "gencode: BINARY"
1334 :     else oper64
1335 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1336 :     fun ibinary(oper16, oper32) =
1337 :     let val oper = case fty of
1338 :     16 => oper16
1339 :     | 32 => oper32
1340 :     | _ => error "gencode: IBINARY"
1341 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1342 :     in case binop of
1343 :     FADD => binary(I.FADDS, I.FADDL)
1344 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1345 :     | FMUL => binary(I.FMULS, I.FMULL)
1346 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1347 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1348 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1349 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1350 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1351 :     end
1352 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1353 :     let fun doit(t1, t2, oper, operP, operRP) =
1354 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1355 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1356 :     *)
1357 :     val n1 = label t1
1358 :     val n2 = label t2
1359 :     in if n1 < n2 andalso n1 <= 7 then
1360 :     (gencode t2;
1361 :     gencode t1;
1362 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1363 :     else if n2 <= n1 andalso n2 <= 7 then
1364 :     (gencode t1;
1365 :     gencode t2;
1366 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1367 :     else
1368 :     let (* both labels > 7 *)
1369 :     val fs = I.FDirect(newFreg())
1370 :     in gencode t2;
1371 :     emit(fstp(fty, fs));
1372 :     gencode t1;
1373 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1374 :     end
1375 :     end
1376 :     in case binop of
1377 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1378 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1379 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1380 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1381 : george 545 | _ => error "gencode.BINARY"
1382 :     end
1383 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1384 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1385 :    
1386 :     (* Generate code for a leaf.
1387 :     * Returns the type and an effective address
1388 :     *)
1389 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1390 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1391 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1392 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1393 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1394 : leunga 565 | leafEA _ = error "leafEA"
1395 :    
1396 : leunga 731 and int2real(ty, e) =
1397 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1398 :     in cleanupCode := !cleanupCode @ cleanup;
1399 :     (INTEGER, ty, ea)
1400 : george 545 end
1401 : leunga 731
1402 :     in gencode(su fexp);
1403 :     emits(!cleanupCode)
1404 : george 545 end (*reduceFexp*)
1405 : leunga 731
1406 :     (*========================================================
1407 :     * This section generates 3-address style floating
1408 :     * point code.
1409 :     *========================================================*)
1410 :    
1411 :     and isize 16 = I.I16
1412 :     | isize 32 = I.I32
1413 :     | isize _ = error "isize"
1414 :    
1415 :     and fstore''(fty, ea, d, mem, an) =
1416 :     (floatingPointUsed := true;
1417 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1418 :     src=foperand(fty, d)},
1419 :     an)
1420 :     )
1421 :    
1422 :     and fload''(fty, ea, mem, d, an) =
1423 :     (floatingPointUsed := true;
1424 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1425 :     dst=RealReg d}, an)
1426 :     )
1427 :    
1428 :     and fiload''(ity, ea, d, an) =
1429 :     (floatingPointUsed := true;
1430 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1431 :     )
1432 :    
1433 :     and fexpr''(e as T.FREG(_,f)) =
1434 :     if isFMemReg f then transFexpr e else f
1435 :     | fexpr'' e = transFexpr e
1436 :    
1437 :     and transFexpr e =
1438 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1439 :    
1440 :     (*
1441 :     * Process a floating point operand. Put operand in register
1442 :     * when possible. The operand should match the given fty.
1443 :     *)
1444 :     and foperand(fty, e as T.FREG(fty', f)) =
1445 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1446 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1447 :     foperand(fty, e) (* nop on the x86 *)
1448 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1449 :     (* fold operand when the precison matches *)
1450 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1451 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1452 :    
1453 :     (*
1454 :     * Process a floating point operand.
1455 :     * Try to fold in a memory operand or conversion from an integer.
1456 :     *)
1457 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1458 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1459 :     (REAL, fty, address(ea, mem), [])
1460 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1461 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1462 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1463 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1464 :    
1465 :     (* Generate binary operator. Since the real binary operators
1466 :     * does not take memory as destination, we also ensure this
1467 :     * does not happen.
1468 :     *)
1469 :     and fbinop(targetFty,
1470 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1471 :     (* Put the mem operand in rsrc *)
1472 :     let val _ = floatingPointUsed := true;
1473 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1474 :     | isMemOpnd(T.FLOAD _) = true
1475 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1476 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1477 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1478 :     | isMemOpnd _ = false
1479 :     val (binOp, ibinOp, lsrc, rsrc) =
1480 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1481 :     else (binOp, ibinOp, lsrc, rsrc)
1482 :     val lsrc = foperand(targetFty, lsrc)
1483 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1484 :     fun dstMustBeFreg f =
1485 :     if targetFty <> 64 then
1486 :     let val tmpR = newFreg()
1487 :     val tmp = I.FPR tmpR
1488 :     in mark(f tmp, an);
1489 :     emit(I.FMOVE{fsize=fsize targetFty,
1490 :     src=tmp, dst=RealReg fd})
1491 :     end
1492 :     else mark(f(RealReg fd), an)
1493 :     in case kind of
1494 :     REAL =>
1495 :     dstMustBeFreg(fn dst =>
1496 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1497 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1498 :     | INTEGER =>
1499 :     (dstMustBeFreg(fn dst =>
1500 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1501 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1502 :     emits code
1503 :     )
1504 :     end
1505 : george 545
1506 : leunga 731 and funop(fty, unOp, src, fd, an) =
1507 :     let val src = foperand(fty, src)
1508 :     in mark(I.FUNOP{fsize=fsize fty,
1509 :     unOp=unOp, src=src, dst=RealReg fd},an)
1510 :     end
1511 :    
1512 :     and doFexpr''(fty, e, fd, an) =
1513 :     case e of
1514 : leunga 744 T.FREG(_,fs) => if C.sameColor(fs,fd) then ()
1515 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1516 :     (* Stupid x86 does everything as 80-bits internally. *)
1517 :    
1518 :     (* Binary operators *)
1519 :     | T.FADD(_, a, b) => fbinop(fty,
1520 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1521 :     a, b, fd, an)
1522 :     | T.FSUB(_, a, b) => fbinop(fty,
1523 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1524 :     a, b, fd, an)
1525 :     | T.FMUL(_, a, b) => fbinop(fty,
1526 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1527 :     a, b, fd, an)
1528 :     | T.FDIV(_, a, b) => fbinop(fty,
1529 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1530 :     a, b, fd, an)
1531 :    
1532 :     (* Unary operators *)
1533 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1534 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1535 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1536 :    
1537 :     (* Load *)
1538 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1539 :    
1540 :     (* Type conversions *)
1541 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1542 :     | T.CVTI2F(_, ty, e) =>
1543 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1544 :     in fiload''(ty, ea, fd, an);
1545 :     emits cleanup
1546 :     end
1547 :    
1548 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1549 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1550 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1551 :     | T.FEXT fexp =>
1552 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1553 :     | _ => error("doFexpr''")
1554 :    
1555 :     (*========================================================
1556 :     * Tie the two styles of fp code generation together
1557 :     *========================================================*)
1558 :     and fstore(fty, ea, d, mem, an) =
1559 :     if enableFastFPMode andalso !fast_floating_point
1560 :     then fstore''(fty, ea, d, mem, an)
1561 :     else fstore'(fty, ea, d, mem, an)
1562 :     and fload(fty, ea, d, mem, an) =
1563 :     if enableFastFPMode andalso !fast_floating_point
1564 :     then fload''(fty, ea, d, mem, an)
1565 :     else fload'(fty, ea, d, mem, an)
1566 :     and fexpr e =
1567 :     if enableFastFPMode andalso !fast_floating_point
1568 :     then fexpr'' e else fexpr' e
1569 :     and doFexpr(fty, e, fd, an) =
1570 :     if enableFastFPMode andalso !fast_floating_point
1571 :     then doFexpr''(fty, e, fd, an)
1572 :     else doFexpr'(fty, e, fd, an)
1573 :    
1574 : leunga 797 (*================================================================
1575 :     * Optimizations for x := x op y
1576 :     * Special optimizations:
1577 :     * Generate a binary operator, result must in memory.
1578 :     * The source must not be in memory
1579 :     *================================================================*)
1580 :     and binaryMem(binOp, src, dst, mem, an) =
1581 :     mark(I.BINARY{binOp=binOp, src=immedOrReg(operand src),
1582 :     dst=address(dst,mem)}, an)
1583 :     and unaryMem(unOp, opnd, mem, an) =
1584 :     mark(I.UNARY{unOp=unOp, opnd=address(opnd,mem)}, an)
1585 :    
1586 :     and isOne(T.LI n) = n = one
1587 :     | isOne _ = false
1588 :    
1589 :     (*
1590 :     * Perform optimizations based on recognizing
1591 :     * x := x op y or
1592 :     * x := y op x
1593 :     * first.
1594 :     *)
1595 :     and store(ty, ea, d, mem, an,
1596 :     {INC,DEC,ADD,SUB,NOT,NEG,SHL,SHR,SAR,OR,AND,XOR},
1597 :     doStore
1598 :     ) =
1599 :     let fun default() = doStore(ea, d, mem, an)
1600 :     fun binary1(t, t', unary, binary, ea', x) =
1601 :     if t = ty andalso t' = ty then
1602 :     if MLTreeUtils.eqRexp(ea, ea') then
1603 :     if isOne x then unaryMem(unary, ea, mem, an)
1604 :     else binaryMem(binary, x, ea, mem, an)
1605 :     else default()
1606 :     else default()
1607 :     fun unary(t,unOp, ea') =
1608 :     if t = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1609 :     unaryMem(unOp, ea, mem, an)
1610 :     else default()
1611 :     fun binary(t,t',binOp,ea',x) =
1612 :     if t = ty andalso t' = ty andalso
1613 :     MLTreeUtils.eqRexp(ea, ea') then
1614 :     binaryMem(binOp, x, ea, mem, an)
1615 :     else default()
1616 :    
1617 :     fun binaryCom1(t,unOp,binOp,x,y) =
1618 :     if t = ty then
1619 :     let fun again() =
1620 :     case y of
1621 :     T.LOAD(ty',ea',_) =>
1622 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1623 :     if isOne x then unaryMem(unOp, ea, mem, an)
1624 :     else binaryMem(binOp,x,ea,mem,an)
1625 :     else default()
1626 :     | _ => default()
1627 :     in case x of
1628 :     T.LOAD(ty',ea',_) =>
1629 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1630 :     if isOne y then unaryMem(unOp, ea, mem, an)
1631 :     else binaryMem(binOp,y,ea,mem,an)
1632 :     else again()
1633 :     | _ => again()
1634 :     end
1635 :     else default()
1636 :    
1637 :     fun binaryCom(t,binOp,x,y) =
1638 :     if t = ty then
1639 :     let fun again() =
1640 :     case y of
1641 :     T.LOAD(ty',ea',_) =>
1642 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1643 :     binaryMem(binOp,x,ea,mem,an)
1644 :     else default()
1645 :     | _ => default()
1646 :     in case x of
1647 :     T.LOAD(ty',ea',_) =>
1648 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1649 :     binaryMem(binOp,y,ea,mem,an)
1650 :     else again()
1651 :     | _ => again()
1652 :     end
1653 :     else default()
1654 :    
1655 :     in case d of
1656 :     T.ADD(t,x,y) => binaryCom1(t,INC,ADD,x,y)
1657 :     | T.SUB(t,T.LOAD(t',ea',_),x) => binary1(t,t',DEC,SUB,ea',x)
1658 :     | T.ORB(t,x,y) => binaryCom(t,OR,x,y)
1659 :     | T.ANDB(t,x,y) => binaryCom(t,AND,x,y)
1660 :     | T.XORB(t,x,y) => binaryCom(t,XOR,x,y)
1661 :     | T.SLL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHL,ea',x)
1662 :     | T.SRL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHR,ea',x)
1663 :     | T.SRA(t,T.LOAD(t',ea',_),x) => binary(t,t',SAR,ea',x)
1664 :     | T.NEG(t,T.LOAD(t',ea',_)) => unary(t,NEG,ea')
1665 :     | T.NOTB(t,T.LOAD(t',ea',_)) => unary(t,NOT,ea')
1666 :     | _ => default()
1667 :     end (* store *)
1668 :    
1669 : george 545 (* generate code for a statement *)
1670 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1671 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1672 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1673 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1674 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1675 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1676 :     | stmt(T.CALL{funct, targets, defs, uses, region, ...}, an) =
1677 : leunga 796 call(funct,targets,defs,uses,region,[],an)
1678 :     | stmt(T.FLOW_TO(T.CALL{funct, targets, defs, uses, region, ...},
1679 :     cutTo), an) =
1680 :     call(funct,targets,defs,uses,region,cutTo,an)
1681 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1682 : leunga 797 | stmt(T.STORE(8, ea, d, mem), an) =
1683 :     store(8, ea, d, mem, an, opcodes8, store8)
1684 :     | stmt(T.STORE(16, ea, d, mem), an) =
1685 :     store(16, ea, d, mem, an, opcodes16, store16)
1686 :     | stmt(T.STORE(32, ea, d, mem), an) =
1687 :     store(32, ea, d, mem, an, opcodes32, store32)
1688 :    
1689 : george 545 | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1690 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1691 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1692 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1693 : george 555 | stmt(T.EXT s, an) =
1694 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1695 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1696 :    
1697 :     and doStmt s = stmt(s, [])
1698 :     and doStmts ss = app doStmt ss
1699 :    
1700 :     and beginCluster' _ =
1701 :     ((* Must be cleared by the client.
1702 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1703 :     *)
1704 : leunga 731 floatingPointUsed := false;
1705 :     trapLabel := NONE;
1706 :     beginCluster 0
1707 :     )
1708 : george 545 and endCluster' a =
1709 : monnier 247 (case !trapLabel
1710 : monnier 411 of NONE => ()
1711 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1712 : monnier 411 (*esac*);
1713 : leunga 731 (* If floating point has been used allocate an extra
1714 :     * register just in case we didn't use any explicit register
1715 :     *)
1716 :     if !floatingPointUsed then (newFreg(); ())
1717 :     else ();
1718 : george 545 endCluster(a)
1719 :     )
1720 :    
1721 :     and reducer() =
1722 :     T.REDUCER{reduceRexp = expr,
1723 :     reduceFexp = fexpr,
1724 :     reduceCCexp = ccExpr,
1725 :     reduceStm = stmt,
1726 :     operand = operand,
1727 :     reduceOperand = reduceOpnd,
1728 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1729 :     emit = mark,
1730 :     instrStream = instrStream,
1731 :     mltreeStream = self()
1732 :     }
1733 :    
1734 :     and self() =
1735 :     S.STREAM
1736 :     { beginCluster= beginCluster',
1737 :     endCluster = endCluster',
1738 :     emit = doStmt,
1739 :     pseudoOp = pseudoOp,
1740 :     defineLabel = defineLabel,
1741 :     entryLabel = entryLabel,
1742 :     comment = comment,
1743 :     annotation = annotation,
1744 : leunga 744 exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1745 : george 545 }
1746 :    
1747 :     in self()
1748 : monnier 247 end
1749 :    
1750 : george 545 end (* functor *)
1751 :    
1752 :     end (* local *)

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