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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 : leunga 797 structure MLTreeUtils : MLTREE_UTILS
43 :     where T = X86Instr.T
44 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
45 : leunga 775 where I = X86Instr
46 : george 545 datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
47 :     val arch : arch ref
48 : leunga 593 val cvti2f :
49 : leunga 815 {ty: X86Instr.T.ty,
50 :     src: X86Instr.operand,
51 :     (* source operand, guaranteed to be non-memory! *)
52 :     an: Annotations.annotations ref (* cluster annotations *)
53 :     } ->
54 : leunga 593 {instrs : X86Instr.instruction list,(* the instructions *)
55 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
56 :     cleanup: X86Instr.instruction list (* cleanup code *)
57 :     }
58 : leunga 731 (* When the following flag is set, we allocate floating point registers
59 :     * directly on the floating point stack
60 :     *)
61 :     val fast_floating_point : bool ref
62 : george 545 ) : sig include MLTREECOMP
63 :     val rewriteMemReg : bool
64 :     end =
65 : monnier 247 struct
66 : leunga 775 structure I = X86Instr
67 :     structure T = I.T
68 : monnier 429 structure S = T.Stream
69 : george 545 structure C = I.C
70 :     structure Shuffle = Shuffle(I)
71 : monnier 247 structure W32 = Word32
72 : george 545 structure LE = I.LabelExp
73 :     structure A = MLRiscAnnotations
74 : monnier 247
75 : leunga 744 type instrStream = (I.instruction,C.cellset) T.stream
76 :     type mltreeStream = (T.stm,T.mlrisc list) T.stream
77 : leunga 565
78 :     datatype kind = REAL | INTEGER
79 : george 545
80 :     structure Gen = MLTreeGen
81 :     (structure T = T
82 :     val intTy = 32
83 :     val naturalWidths = [32]
84 :     datatype rep = SE | ZE | NEITHER
85 :     val rep = NEITHER
86 :     )
87 :    
88 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
89 : monnier 247
90 : george 545 (* Should we perform automatic MemReg translation?
91 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
92 :     *)
93 :     val rewriteMemReg = rewriteMemReg
94 : leunga 731
95 :     (* The following hardcoded *)
96 : leunga 744 fun isMemReg r = rewriteMemReg andalso
97 :     let val r = C.registerNum r
98 :     in r >= 8 andalso r < 32
99 :     end
100 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
101 : leunga 744 then let val r = C.registerNum r
102 :     in r >= 8 andalso r < 32 end
103 : leunga 731 else true
104 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
105 :     let val r = C.registerNum r
106 :     in r >= 8 andalso r < 32 end
107 :     )
108 : monnier 247
109 : george 555 val ST0 = C.ST 0
110 :     val ST7 = C.ST 7
111 : leunga 797 val one = T.I.int_1
112 : george 555
113 : leunga 797 val opcodes8 = {INC=I.INCB,DEC=I.DECB,ADD=I.ADDB,SUB=I.SUBB,
114 :     NOT=I.NOTB,NEG=I.NEGB,
115 :     SHL=I.SHLB,SHR=I.SHRB,SAR=I.SARB,
116 :     OR=I.ORB,AND=I.ANDB,XOR=I.XORB}
117 :     val opcodes16 = {INC=I.INCW,DEC=I.DECW,ADD=I.ADDW,SUB=I.SUBW,
118 :     NOT=I.NOTW,NEG=I.NEGW,
119 :     SHL=I.SHLW,SHR=I.SHRW,SAR=I.SARW,
120 :     OR=I.ORW,AND=I.ANDW,XOR=I.XORW}
121 :     val opcodes32 = {INC=I.INCL,DEC=I.DECL,ADD=I.ADDL,SUB=I.SUBL,
122 :     NOT=I.NOTL,NEG=I.NEGL,
123 :     SHL=I.SHLL,SHR=I.SHRL,SAR=I.SARL,
124 :     OR=I.ORL,AND=I.ANDL,XOR=I.XORL}
125 :    
126 : george 545 (*
127 :     * The code generator
128 :     *)
129 : monnier 411 fun selectInstructions
130 : george 545 (instrStream as
131 : leunga 815 S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,getAnnotations,
132 : leunga 744 beginCluster,endCluster,exitBlock,comment,...}) =
133 : george 545 let exception EA
134 : monnier 411
135 : george 545 (* label where a trap is generated -- one per cluster *)
136 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
137 : monnier 247
138 : leunga 731 (* flag floating point generation *)
139 :     val floatingPointUsed = ref false
140 :    
141 : george 545 (* effective address of an integer register *)
142 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
143 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
144 : monnier 411
145 : george 545 (* Add an overflow trap *)
146 :     fun trap() =
147 :     let val jmp =
148 :     case !trapLabel of
149 :     NONE => let val label = Label.newLabel "trap"
150 :     val jmp = I.JCC{cond=I.O,
151 : leunga 775 opnd=I.ImmedLabel(T.LABEL label)}
152 : george 545 in trapLabel := SOME(jmp, label); jmp end
153 :     | SOME(jmp, _) => jmp
154 :     in emit jmp end
155 : monnier 411
156 : george 545 val newReg = C.newReg
157 :     val newFreg = C.newFreg
158 : monnier 247
159 : leunga 731 fun fsize 32 = I.FP32
160 :     | fsize 64 = I.FP64
161 :     | fsize 80 = I.FP80
162 :     | fsize _ = error "fsize"
163 :    
164 : george 545 (* mark an expression with a list of annotations *)
165 :     fun mark'(i,[]) = i
166 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
167 : monnier 247
168 : george 545 (* annotate an expression and emit it *)
169 :     fun mark(i,an) = emit(mark'(i,an))
170 : monnier 247
171 : leunga 731 val emits = app emit
172 :    
173 : george 545 (* emit parallel copies for integers
174 :     * Translates parallel copies that involve memregs into
175 :     * individual copies.
176 :     *)
177 :     fun copy([], [], an) = ()
178 :     | copy(dst, src, an) =
179 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
180 : leunga 744 if C.sameColor(rd,rs) then [] else
181 : george 545 let val tmpR = I.Direct(newReg())
182 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
183 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
184 :     end
185 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
186 : leunga 744 if C.sameColor(rd,rs) then []
187 : george 545 else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
188 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
189 :     in
190 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
191 : leunga 744 {tmp=SOME(I.Direct(newReg())),
192 : george 545 dst=dst, src=src})
193 :     end
194 :    
195 :     (* conversions *)
196 :     val itow = Word.fromInt
197 :     val wtoi = Word.toInt
198 : george 761 fun toInt32 i = T.I.toInt32(32, i)
199 : george 545 val w32toi32 = Word32.toLargeIntX
200 :     val i32tow32 = Word32.fromLargeInt
201 : monnier 247
202 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
203 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
204 : monnier 247
205 : george 545 (* some useful registers *)
206 :     val eax = I.Direct(C.eax)
207 :     val ecx = I.Direct(C.ecx)
208 :     val edx = I.Direct(C.edx)
209 : monnier 247
210 : leunga 775 fun immedLabel lab = I.ImmedLabel(T.LABEL lab)
211 : george 545
212 :     (* Is the expression zero? *)
213 : george 761 fun isZero(T.LI z) = T.I.isZero z
214 : george 545 | isZero(T.MARK(e,a)) = isZero e
215 :     | isZero _ = false
216 :     (* Does the expression set the zero bit?
217 :     * WARNING: we assume these things are not optimized out!
218 :     *)
219 :     fun setZeroBit(T.ANDB _) = true
220 :     | setZeroBit(T.ORB _) = true
221 :     | setZeroBit(T.XORB _) = true
222 :     | setZeroBit(T.SRA _) = true
223 :     | setZeroBit(T.SRL _) = true
224 :     | setZeroBit(T.SLL _) = true
225 : leunga 695 | setZeroBit(T.SUB _) = true
226 :     | setZeroBit(T.ADDT _) = true
227 :     | setZeroBit(T.SUBT _) = true
228 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
229 :     | setZeroBit _ = false
230 : monnier 247
231 : leunga 695 fun setZeroBit2(T.ANDB _) = true
232 :     | setZeroBit2(T.ORB _) = true
233 :     | setZeroBit2(T.XORB _) = true
234 :     | setZeroBit2(T.SRA _) = true
235 :     | setZeroBit2(T.SRL _) = true
236 :     | setZeroBit2(T.SLL _) = true
237 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
238 :     | setZeroBit2(T.SUB _) = true
239 :     | setZeroBit2(T.ADDT _) = true
240 :     | setZeroBit2(T.SUBT _) = true
241 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
242 :     | setZeroBit2 _ = false
243 :    
244 : leunga 731 (* emit parallel copies for floating point
245 :     * Normal version.
246 :     *)
247 :     fun fcopy'(fty, [], [], _) = ()
248 :     | fcopy'(fty, dst as [_], src as [_], an) =
249 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
250 : leunga 731 | fcopy'(fty, dst, src, an) =
251 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
252 : monnier 247
253 : leunga 731 (* emit parallel copies for floating point.
254 :     * Fast version.
255 :     * Translates parallel copies that involve memregs into
256 :     * individual copies.
257 :     *)
258 :    
259 :     fun fcopy''(fty, [], [], _) = ()
260 :     | fcopy''(fty, dst, src, an) =
261 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
262 :     let val fsize = fsize fty
263 :     fun mvInstr{dst, src} = [I.FMOVE{fsize=fsize, src=src, dst=dst}]
264 :     in
265 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
266 : leunga 744 {tmp=case dst of
267 : leunga 731 [_] => NONE
268 :     | _ => SOME(I.FPR(newReg())),
269 :     dst=dst, src=src})
270 :     end
271 :     else
272 :     mark(I.FCOPY{dst=dst,src=src,tmp=
273 :     case dst of
274 :     [_] => NONE
275 :     | _ => SOME(I.FPR(newFreg()))}, an)
276 :    
277 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
278 :     then fcopy'' x else fcopy' x
279 :    
280 : george 545 (* Translates MLTREE condition code to x86 condition code *)
281 :     fun cond T.LT = I.LT | cond T.LTU = I.B
282 :     | cond T.LE = I.LE | cond T.LEU = I.BE
283 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
284 :     | cond T.GE = I.GE | cond T.GEU = I.AE
285 :     | cond T.GT = I.GT | cond T.GTU = I.A
286 : monnier 247
287 : leunga 815 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
288 :    
289 : george 545 (* Move and annotate *)
290 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
291 : leunga 744 if C.sameColor(s,d) then ()
292 : george 545 else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
293 : leunga 815 | move'(I.Immed 0, dst as I.Direct d, an) =
294 :     mark(I.BINARY{binOp=I.XORL, src=dst, dst=dst}, an)
295 : george 545 | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
296 : monnier 247
297 : george 545 (* Move only! *)
298 :     fun move(src, dst) = move'(src, dst, [])
299 : monnier 247
300 : george 545 val readonly = I.Region.readonly
301 : monnier 247
302 : george 545 (*
303 : george 761 * Compute an effective address.
304 : george 545 *)
305 : george 761 fun address(ea, mem) = let
306 : george 545 (* Keep building a bigger and bigger effective address expressions
307 :     * The input is a list of trees
308 :     * b -- base
309 :     * i -- index
310 :     * s -- scale
311 :     * d -- immed displacement
312 :     *)
313 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
314 :     | doEA(t::trees, b, i, s, d) =
315 :     (case t of
316 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
317 : leunga 775 | T.CONST _ => doEALabel(trees, t, b, i, s, d)
318 :     | T.LABEL _ => doEALabel(trees, t, b, i, s, d)
319 :     | T.LABEXP le => doEALabel(trees, le, b, i, s, d)
320 : george 545 | T.ADD(32, t1, t2 as T.REG(_,r)) =>
321 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
322 :     else doEA(t1::t2::trees, b, i, s, d)
323 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
324 :     | T.SUB(32, t1, T.LI n) =>
325 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
326 :     | T.SLL(32, t1, T.LI n) => let
327 :     val n = T.I.toInt(32, n)
328 :     in
329 :     case n
330 :     of 0 => displace(trees, t1, b, i, s, d)
331 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
332 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
333 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
334 :     | _ => displace(trees, t, b, i, s, d)
335 :     end
336 : george 545 | t => displace(trees, t, b, i, s, d)
337 :     )
338 : monnier 247
339 : george 545 (* Add an immed constant *)
340 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
341 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
342 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
343 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
344 : leunga 775 doEA(trees, b, i, s,
345 :     I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, n)))))
346 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
347 : monnier 247
348 : george 545 (* Add a label expression *)
349 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
350 :     doEA(trees, b, i, s, I.ImmedLabel le)
351 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
352 :     doEA(trees, b, i, s,
353 : leunga 775 I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, m))))
354 : george 545 handle Overflow => error "doEALabel: constant too large")
355 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
356 : leunga 775 doEA(trees, b, i, s, I.ImmedLabel(T.ADD(32,le,le')))
357 : george 545 | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
358 : monnier 247
359 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
360 :     | makeAddressingMode(SOME base, NONE, _, disp) =
361 :     I.Displace{base=base, disp=disp, mem=mem}
362 :     | makeAddressingMode(base, SOME index, scale, disp) =
363 : george 761 I.Indexed{base=base, index=index, scale=scale,
364 : george 545 disp=disp, mem=mem}
365 : monnier 247
366 : george 545 (* generate code for tree and ensure that it is not in %esp *)
367 :     and exprNotEsp tree =
368 :     let val r = expr tree
369 : leunga 744 in if C.sameColor(r, C.esp) then
370 : george 545 let val tmp = newReg()
371 :     in move(I.Direct r, I.Direct tmp); tmp end
372 :     else r
373 :     end
374 : monnier 247
375 : george 545 (* Add a base register *)
376 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
377 :     doEA(trees, SOME(expr t), i, s, d)
378 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
379 :     (* make t the index, but make sure that it is not %esp! *)
380 :     let val i = expr t
381 : leunga 744 in if C.sameColor(i, C.esp) then
382 : george 545 (* swap base and index *)
383 : leunga 744 if C.sameColor(base, C.esp) then
384 : george 545 doEA(trees, SOME i, b, 0, d)
385 :     else (* base and index = %esp! *)
386 :     let val index = newReg()
387 :     in move(I.Direct i, I.Direct index);
388 :     doEA(trees, b, SOME index, 0, d)
389 :     end
390 :     else
391 :     doEA(trees, b, SOME i, 0, d)
392 :     end
393 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
394 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
395 :     in doEA(trees, SOME b, i, s, d) end
396 : monnier 247
397 : george 545 (* Add an indexed register *)
398 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
399 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
400 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
401 :     doEA(trees, SOME(expr t0), i, s, d)
402 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
403 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
404 :     in doEA(trees, SOME b, i, s, d) end
405 :    
406 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
407 :     I.Immed _ => raise EA
408 :     | I.ImmedLabel le => I.LabelEA le
409 :     | ea => ea
410 :     end (* address *)
411 : monnier 247
412 : george 545 (* reduce an expression into an operand *)
413 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
414 : leunga 775 | operand(x as (T.CONST _ | T.LABEL _)) = I.ImmedLabel x
415 :     | operand(T.LABEXP le) = I.ImmedLabel le
416 : george 545 | operand(T.REG(_,r)) = IntReg r
417 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
418 :     | operand(t) = I.Direct(expr t)
419 : monnier 247
420 : george 545 and moveToReg(opnd) =
421 :     let val dst = I.Direct(newReg())
422 :     in move(opnd, dst); dst
423 :     end
424 : monnier 247
425 : george 545 and reduceOpnd(I.Direct r) = r
426 :     | reduceOpnd opnd =
427 :     let val dst = newReg()
428 :     in move(opnd, I.Direct dst); dst
429 :     end
430 : monnier 247
431 : george 545 (* ensure that the operand is either an immed or register *)
432 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
433 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
434 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
435 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
436 :     | immedOrReg opnd = opnd
437 : monnier 247
438 : george 545 and isImmediate(I.Immed _) = true
439 :     | isImmediate(I.ImmedLabel _) = true
440 :     | isImmediate _ = false
441 : monnier 247
442 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
443 :    
444 :     and isMemOpnd opnd =
445 :     (case opnd of
446 :     I.Displace _ => true
447 :     | I.Indexed _ => true
448 :     | I.MemReg _ => true
449 :     | I.LabelEA _ => true
450 : george 555 | I.FDirect f => true
451 : george 545 | _ => false
452 :     )
453 :    
454 :     (*
455 :     * Compute an integer expression and put the result in
456 :     * the destination register rd.
457 :     *)
458 :     and doExpr(exp, rd : I.C.cell, an) =
459 :     let val rdOpnd = IntReg rd
460 : monnier 247
461 : leunga 744 fun equalRd(I.Direct r) = C.sameColor(r, rd)
462 :     | equalRd(I.MemReg r) = C.sameColor(r, rd)
463 : george 545 | equalRd _ = false
464 : monnier 247
465 : george 545 (* Emit a binary operator. If the destination is
466 :     * a memReg, do something smarter.
467 :     *)
468 :     fun genBinary(binOp, opnd1, opnd2) =
469 :     if isMemReg rd andalso
470 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
471 :     equalRd(opnd2)
472 :     then
473 :     let val tmpR = newReg()
474 :     val tmp = I.Direct tmpR
475 :     in move(opnd1, tmp);
476 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
477 :     move(tmp, rdOpnd)
478 :     end
479 :     else
480 :     (move(opnd1, rdOpnd);
481 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
482 :     )
483 : monnier 247
484 : george 545 (* Generate a binary operator; it may commute *)
485 :     fun binaryComm(binOp, e1, e2) =
486 :     let val (opnd1, opnd2) =
487 :     case (operand e1, operand e2) of
488 :     (x as I.Immed _, y) => (y, x)
489 :     | (x as I.ImmedLabel _, y) => (y, x)
490 :     | (x, y as I.Direct _) => (y, x)
491 :     | (x, y) => (x, y)
492 :     in genBinary(binOp, opnd1, opnd2)
493 :     end
494 :    
495 :     (* Generate a binary operator; non-commutative *)
496 :     fun binary(binOp, e1, e2) =
497 :     genBinary(binOp, operand e1, operand e2)
498 :    
499 :     (* Generate a unary operator *)
500 :     fun unary(unOp, e) =
501 :     let val opnd = operand e
502 :     in if isMemReg rd andalso isMemOpnd opnd then
503 :     let val tmp = I.Direct(newReg())
504 :     in move(opnd, tmp); move(tmp, rdOpnd)
505 :     end
506 :     else move(opnd, rdOpnd);
507 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
508 :     end
509 :    
510 :     (* Generate shifts; the shift
511 :     * amount must be a constant or in %ecx *)
512 :     fun shift(opcode, e1, e2) =
513 :     let val (opnd1, opnd2) = (operand e1, operand e2)
514 :     in case opnd2 of
515 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
516 :     | _ =>
517 :     if equalRd(opnd2) then
518 :     let val tmpR = newReg()
519 :     val tmp = I.Direct tmpR
520 :     in move(opnd1, tmp);
521 :     move(opnd2, ecx);
522 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
523 :     move(tmp, rdOpnd)
524 :     end
525 :     else
526 :     (move(opnd1, rdOpnd);
527 :     move(opnd2, ecx);
528 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
529 :     )
530 :     end
531 :    
532 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
533 :     fun divrem(signed, overflow, e1, e2, resultReg) =
534 :     let val (opnd1, opnd2) = (operand e1, operand e2)
535 :     val _ = move(opnd1, eax)
536 : leunga 815 val oper = if signed then (emit(I.CDQ); I.IDIVL1)
537 :     else (zero edx; I.DIVL1)
538 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
539 :     move(resultReg, rdOpnd);
540 :     if overflow then trap() else ()
541 :     end
542 :    
543 :     (* Optimize the special case for division *)
544 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
545 :     val n = toInt32 n'
546 :     val w = T.I.toWord32(32, n')
547 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
548 : george 545 fun log2 n = (* n must be > 0!!! *)
549 :     let fun loop(0w1,pow) = pow
550 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
551 : george 545 in loop(n,0) end
552 :     in if n > 1 andalso isPowerOf2 w then
553 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
554 : george 545 in if signed then
555 :     (* signed; simulate round towards zero *)
556 :     let val label = Label.newLabel ""
557 :     val reg1 = expr e1
558 :     val opnd1 = I.Direct reg1
559 :     in if setZeroBit e1 then ()
560 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
561 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
562 :     emit(if n = 2 then
563 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
564 :     else
565 :     I.BINARY{binOp=I.ADDL,
566 : george 761 src=I.Immed(n - 1),
567 : george 545 dst=opnd1});
568 :     defineLabel label;
569 :     shift(I.SARL, T.REG(32, reg1), pow)
570 :     end
571 :     else (* unsigned *)
572 :     shift(I.SHRL, e1, pow)
573 :     end
574 :     else
575 :     (* note the only way we can overflow is if
576 :     * n = 0 or n = -1
577 :     *)
578 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
579 :     e1, e2, eax)
580 :     end
581 :     | divide(signed, overflow, e1, e2) =
582 :     divrem(signed, overflow, e1, e2, eax)
583 : monnier 247
584 : george 545 fun rem(signed, overflow, e1, e2) =
585 :     divrem(signed, overflow, e1, e2, edx)
586 : leunga 815
587 :     (* Makes sure the destination must be a register *)
588 :     fun dstMustBeReg f =
589 :     if isMemReg rd then
590 :     let val tmpR = newReg()
591 :     val tmp = I.Direct(tmpR)
592 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
593 :     else f(rd, rdOpnd)
594 :    
595 : george 545 (* unsigned integer multiplication *)
596 :     fun uMultiply(e1, e2) =
597 :     (* note e2 can never be (I.Direct edx) *)
598 :     (move(operand e1, eax);
599 : leunga 815 mark(I.MULTDIV{multDivOp=I.MULL1,
600 : george 545 src=regOrMem(operand e2)},an);
601 :     move(eax, rdOpnd)
602 :     )
603 :    
604 :     (* signed integer multiplication:
605 :     * The only forms that are allowed that also sets the
606 :     * OF and CF flags are:
607 :     *
608 : leunga 815 * (dst) (src1) (src2)
609 : george 545 * imul r32, r32/m32, imm8
610 : leunga 815 * (dst) (src)
611 : george 545 * imul r32, imm8
612 :     * imul r32, imm32
613 : leunga 815 * imul r32, r32/m32
614 :     * Note: destination must be a register!
615 : george 545 *)
616 :     fun multiply(e1, e2) =
617 : leunga 815 dstMustBeReg(fn (rd, rdOpnd) =>
618 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _) =
619 :     (move(i1, rdOpnd);
620 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=i2},an))
621 :     | doit(rm, i2 as I.Immed _) = doit(i2, rm)
622 :     | doit(imm as I.Immed(i), rm) =
623 :     mark(I.MUL3{dst=rd, src1=rm, src2=i},an)
624 :     | doit(r1 as I.Direct _, r2 as I.Direct _) =
625 :     (move(r1, rdOpnd);
626 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=r2},an))
627 :     | doit(r1 as I.Direct _, rm) =
628 :     (move(r1, rdOpnd);
629 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm},an))
630 :     | doit(rm, r as I.Direct _) = doit(r, rm)
631 :     | doit(rm1, rm2) =
632 : george 545 if equalRd rm2 then
633 :     let val tmpR = newReg()
634 :     val tmp = I.Direct tmpR
635 :     in move(rm1, tmp);
636 : leunga 815 mark(I.BINARY{binOp=I.IMULL, dst=tmp, src=rm2},an);
637 :     move(tmp, rdOpnd)
638 : george 545 end
639 :     else
640 : leunga 815 (move(rm1, rdOpnd);
641 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm2},an)
642 : george 545 )
643 :     val (opnd1, opnd2) = (operand e1, operand e2)
644 : leunga 815 in doit(opnd1, opnd2)
645 : george 545 end
646 : leunga 815 )
647 : monnier 247
648 : george 545 (* Emit a load instruction; makes sure that the destination
649 :     * is a register
650 :     *)
651 :     fun genLoad(mvOp, ea, mem) =
652 :     dstMustBeReg(fn (_, dst) =>
653 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
654 :    
655 :     (* Generate a zero extended loads *)
656 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
657 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
658 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
659 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
660 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
661 :    
662 :     (* Generate a sign extended loads *)
663 :    
664 :     (* Generate setcc instruction:
665 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
666 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
667 :     * Note that we have to use eax as the destination of the
668 :     * setcc because it only works on the registers
669 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
670 :     * are inaccessible in 32 bit mode.
671 : george 545 *)
672 :     fun setcc(ty, cc, t1, t2, yes, no) =
673 : leunga 583 let val (cc, yes, no) =
674 :     if yes > no then (cc, yes, no)
675 :     else (T.Basis.negateCond cc, no, yes)
676 : george 545 in (* Clear the destination first.
677 :     * This this because stupid SETcc
678 :     * only writes to the low order
679 :     * byte. That's Intel architecture, folks.
680 :     *)
681 : leunga 695 case (yes, no, cc) of
682 :     (1, 0, T.LT) =>
683 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
684 :     in move(tmp, rdOpnd);
685 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
686 :     end
687 :     | (1, 0, T.GT) =>
688 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
689 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
690 :     move(tmp, rdOpnd);
691 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
692 :     end
693 :     | (1, 0, _) => (* normal case *)
694 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
695 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
696 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
697 : leunga 583 move(eax, rdOpnd)
698 :     end
699 : leunga 695 | (C1, C2, _) =>
700 : george 545 (* general case;
701 : leunga 583 * from the Intel optimization guide p3-5
702 :     *)
703 : leunga 695 let val _ = zero eax;
704 :     val cc = cmp(true, ty, cc, t1, t2, [])
705 : leunga 583 in case C1-C2 of
706 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
707 :     let val (base,scale) =
708 :     case D of
709 :     1 => (NONE, 0)
710 :     | 2 => (NONE, 1)
711 :     | 3 => (SOME C.eax, 1)
712 :     | 4 => (NONE, 2)
713 :     | 5 => (SOME C.eax, 2)
714 :     | 8 => (NONE, 3)
715 :     | 9 => (SOME C.eax, 3)
716 :     val addr = I.Indexed{base=base,
717 :     index=C.eax,
718 :     scale=scale,
719 :     disp=I.Immed C2,
720 : george 545 mem=readonly}
721 : leunga 583 val tmpR = newReg()
722 :     val tmp = I.Direct tmpR
723 :     in emit(I.SET{cond=cond cc, opnd=eax});
724 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
725 :     move(tmp, rdOpnd)
726 :     end
727 :     | D =>
728 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
729 :     opnd=eax});
730 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
731 :     emit(I.BINARY{binOp=I.ANDL,
732 :     src=I.Immed D, dst=eax});
733 :     if C2 = 0 then
734 :     move(eax, rdOpnd)
735 :     else
736 :     let val tmpR = newReg()
737 :     val tmp = I.Direct tmpR
738 :     in mark(I.LEA{addr=
739 :     I.Displace{
740 :     base=C.eax,
741 :     disp=I.Immed C2,
742 :     mem=readonly},
743 :     r32=tmpR}, an);
744 :     move(tmp, rdOpnd)
745 :     end
746 :     )
747 :     end
748 : george 545 end (* setcc *)
749 :    
750 :     (* Generate cmovcc instruction.
751 :     * on Pentium Pro and Pentium II only
752 :     *)
753 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
754 :     let fun genCmov(dstR, _) =
755 :     let val _ = doExpr(no, dstR, []) (* false branch *)
756 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
757 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
758 :     end
759 :     in dstMustBeReg genCmov
760 :     end
761 :    
762 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
763 : monnier 247
764 : leunga 606 (* Add n to rd *)
765 :     fun addN n =
766 :     let val n = operand n
767 :     val src = if isMemReg rd then immedOrReg n else n
768 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
769 :    
770 : george 545 (* Generate addition *)
771 :     fun addition(e1, e2) =
772 : leunga 606 case e1 of
773 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e2
774 :     else addition1(e1,e2)
775 : leunga 606 | _ => addition1(e1,e2)
776 :     and addition1(e1, e2) =
777 :     case e2 of
778 : leunga 744 T.REG(_,rs) => if C.sameColor(rs,rd) then addN e1
779 :     else addition2(e1,e2)
780 : leunga 606 | _ => addition2(e1,e2)
781 :     and addition2(e1,e2) =
782 : george 545 (dstMustBeReg(fn (dstR, _) =>
783 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
784 :     handle EA => binaryComm(I.ADDL, e1, e2))
785 : monnier 247
786 :    
787 : george 545 in case exp of
788 :     T.REG(_,rs) =>
789 :     if isMemReg rs andalso isMemReg rd then
790 :     let val tmp = I.Direct(newReg())
791 : leunga 731 in move'(I.MemReg rs, tmp, an);
792 : george 545 move'(tmp, rdOpnd, [])
793 :     end
794 :     else move'(IntReg rs, rdOpnd, an)
795 : george 761 | T.LI z => let
796 :     val n = toInt32 z
797 :     in
798 :     if n=0 then
799 :     (* As per Fermin's request, special optimization for rd := 0.
800 :     * Currently we don't bother with the size.
801 :     *)
802 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
803 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
804 :     else
805 :     move'(I.Immed(n), rdOpnd, an)
806 :     end
807 : leunga 775 | (T.CONST _ | T.LABEL _) =>
808 :     move'(I.ImmedLabel exp, rdOpnd, an)
809 :     | T.LABEXP le => move'(I.ImmedLabel le, rdOpnd, an)
810 : monnier 247
811 : george 545 (* 32-bit addition *)
812 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
813 :     val n = toInt32 n
814 :     in
815 :     case n
816 :     of 1 => unary(I.INCL, e1)
817 :     | ~1 => unary(I.DECL, e1)
818 :     | _ => addition(e1, e2)
819 :     end
820 :     | T.ADD(32, e1 as T.LI n, e2) => let
821 :     val n = toInt32 n
822 :     in
823 :     case n
824 :     of 1 => unary(I.INCL, e2)
825 :     | ~1 => unary(I.DECL, e2)
826 :     | _ => addition(e1, e2)
827 :     end
828 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
829 : monnier 247
830 : leunga 695 (* 32-bit addition but set the flag!
831 :     * This is a stupid hack for now.
832 :     *)
833 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
834 :     val n = T.I.toInt(32, n)
835 :     in
836 :     if n=1 then unary(I.INCL, e)
837 :     else if n = ~1 then unary(I.DECL, e)
838 :     else binaryComm(I.ADDL, e, e1)
839 :     end
840 :     | T.ADD(0, e1 as T.LI n, e) => let
841 :     val n = T.I.toInt(32, n)
842 :     in
843 :     if n=1 then unary(I.INCL, e)
844 :     else if n = ~1 then unary(I.DECL, e)
845 :     else binaryComm(I.ADDL, e1, e)
846 :     end
847 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
848 :    
849 : george 545 (* 32-bit subtraction *)
850 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
851 :     val n = toInt32 n
852 :     in
853 :     case n
854 :     of 0 => doExpr(e1, rd, an)
855 :     | 1 => unary(I.DECL, e1)
856 :     | ~1 => unary(I.INCL, e1)
857 :     | _ => binary(I.SUBL, e1, e2)
858 :     end
859 :     | T.SUB(32, e1 as T.LI n, e2) =>
860 :     if T.I.isZero n then unary(I.NEGL, e2)
861 :     else binary(I.SUBL, e1, e2)
862 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
863 : monnier 247
864 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
865 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
866 :     | T.REMU(32, x, y) => rem(false, false, x, y)
867 : monnier 247
868 : george 545 | T.MULS(32, x, y) => multiply(x, y)
869 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
870 :     | T.REMS(32, x, y) => rem(true, false, x, y)
871 : monnier 247
872 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
873 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
874 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
875 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
876 :     | T.REMT(32, x, y) => rem(true, true, x, y)
877 : monnier 247
878 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
879 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
880 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
881 :     | T.NOTB(32, x) => unary(I.NOTL, x)
882 : monnier 247
883 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
884 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
885 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
886 : monnier 247
887 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
888 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
889 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
890 : monnier 498
891 : leunga 776 | T.SX(32,8,T.LOAD(8,ea,mem)) => load8s(ea, mem)
892 :     | T.SX(32,16,T.LOAD(16,ea,mem)) => load16s(ea, mem)
893 :     | T.ZX(32,8,T.LOAD(8,ea,mem)) => load8(ea, mem)
894 : leunga 779 | T.ZX(32,16,T.LOAD(16,ea,mem)) => load16(ea, mem)
895 : leunga 776
896 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
897 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
898 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
899 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
900 :     Pentium => unknownExp exp
901 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
902 :     )
903 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
904 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
905 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
906 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
907 : george 555 | T.REXT e =>
908 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
909 : george 545 (* simplify and try again *)
910 :     | exp => unknownExp exp
911 :     end (* doExpr *)
912 : monnier 247
913 : george 545 (* generate an expression and return its result register
914 :     * If rewritePseudo is on, the result is guaranteed to be in a
915 :     * non memReg register
916 :     *)
917 :     and expr(exp as T.REG(_, rd)) =
918 :     if isMemReg rd then genExpr exp else rd
919 :     | expr exp = genExpr exp
920 : monnier 247
921 : george 545 and genExpr exp =
922 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
923 : monnier 247
924 : george 545 (* Compare an expression with zero.
925 :     * On the x86, TEST is superior to AND for doing the same thing,
926 :     * since it doesn't need to write out the result in a register.
927 :     *)
928 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
929 : george 545 (case ty of
930 : leunga 695 8 => test(I.TESTB, a, b, an)
931 :     | 16 => test(I.TESTW, a, b, an)
932 :     | 32 => test(I.TESTL, a, b, an)
933 :     | _ => doExpr(e, newReg(), an);
934 :     cc)
935 :     | cmpWithZero(cc, e, an) =
936 :     let val e =
937 :     case e of (* hack to disable the lea optimization XXX *)
938 :     T.ADD(_, a, b) => T.ADD(0, a, b)
939 :     | e => e
940 :     in doExpr(e, newReg(), an); cc end
941 : monnier 247
942 : george 545 (* Emit a test.
943 :     * The available modes are
944 :     * r/m, r
945 :     * r/m, imm
946 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
947 :     * When anding an operand with a constant
948 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
949 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
950 :     * this works for memory operands too. However, with TESTB, it is
951 :     * not possible to use registers other than
952 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
953 :     * perform register allocation first, and if the operand registers
954 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
955 :     * by TESTB.
956 :     *)
957 : leunga 695 and test(testopcode, a, b, an) =
958 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
959 :     (* translate r, r/m => r/m, r *)
960 :     val (opnd1, opnd2) =
961 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
962 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
963 : george 545 end
964 : monnier 247
965 : leunga 815 (* %eflags <- src *)
966 :     and moveToEflags src =
967 :     if C.sameColor(src, C.eflags) then ()
968 :     else (move(I.Direct src, eax); emit(I.LAHF))
969 :    
970 :     (* dst <- %eflags *)
971 :     and moveFromEflags dst =
972 :     if C.sameColor(dst, C.eflags) then ()
973 :     else (emit(I.SAHF); move(eax, I.Direct dst))
974 :    
975 : george 545 (* generate a condition code expression
976 : leunga 744 * The zero is for setting the condition code!
977 :     * I have no idea why this is used.
978 :     *)
979 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
980 : leunga 815 (cmp(false, ty, cc, t1, t2, an);
981 :     moveFromEflags rd
982 :     )
983 :     | doCCexpr(T.CC(cond,rs), rd, an) =
984 :     if C.sameColor(rs,C.eflags) orelse C.sameColor(rd,C.eflags) then
985 :     (moveToEflags rs; moveFromEflags rd)
986 : leunga 744 else
987 : leunga 815 move'(I.Direct rs, I.Direct rd, an)
988 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
989 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
990 :     | doCCexpr(T.CCEXT e, cd, an) =
991 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
992 : george 545 | doCCexpr _ = error "doCCexpr"
993 : monnier 247
994 : george 545 and ccExpr e = error "ccExpr"
995 : monnier 247
996 : george 545 (* generate a comparison and sets the condition code;
997 :     * return the actual cc used. If the flag swapable is true,
998 :     * we can also reorder the operands.
999 :     *)
1000 :     and cmp(swapable, ty, cc, t1, t2, an) =
1001 : leunga 695 (* == and <> can be always be reordered *)
1002 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
1003 :     in (* Sometimes the comparison is not necessary because
1004 :     * the bits are already set!
1005 :     *)
1006 :     if isZero t1 andalso setZeroBit2 t2 then
1007 :     if swapable then
1008 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
1009 :     else (* can't reorder the comparison! *)
1010 :     genCmp(ty, false, cc, t1, t2, an)
1011 :     else if isZero t2 andalso setZeroBit2 t1 then
1012 :     cmpWithZero(cc, t1, an)
1013 :     else genCmp(ty, swapable, cc, t1, t2, an)
1014 :     end
1015 : monnier 247
1016 : george 545 (* Give a and b which are the operands to a comparison (or test)
1017 :     * Return the appropriate condition code and operands.
1018 :     * The available modes are:
1019 :     * r/m, imm
1020 :     * r/m, r
1021 :     * r, r/m
1022 :     *)
1023 :     and commuteComparison(cc, swapable, a, b) =
1024 :     let val (opnd1, opnd2) = (operand a, operand b)
1025 :     in (* Try to fold in the operands whenever possible *)
1026 :     case (isImmediate opnd1, isImmediate opnd2) of
1027 :     (true, true) => (cc, moveToReg opnd1, opnd2)
1028 :     | (true, false) =>
1029 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
1030 :     else (cc, moveToReg opnd1, opnd2)
1031 :     | (false, true) => (cc, opnd1, opnd2)
1032 :     | (false, false) =>
1033 :     (case (opnd1, opnd2) of
1034 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1035 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1036 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1037 :     )
1038 :     end
1039 :    
1040 :     (* generate a real comparison; return the real cc used *)
1041 :     and genCmp(ty, swapable, cc, a, b, an) =
1042 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1043 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1044 :     end
1045 : monnier 247
1046 : george 545 (* generate code for jumps *)
1047 : leunga 775 and jmp(lexp as T.LABEL lab, labs, an) =
1048 : george 545 mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1049 : leunga 775 | jmp(T.LABEXP le, labs, an) = mark(I.JMP(I.ImmedLabel le, labs), an)
1050 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1051 : george 545
1052 :     (* convert mlrisc to cellset:
1053 :     *)
1054 :     and cellset mlrisc =
1055 : leunga 744 let val addCCReg = C.CellSet.add
1056 : george 545 fun g([],acc) = acc
1057 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1058 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1059 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1060 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1061 :     | g(_::regs, acc) = g(regs, acc)
1062 :     in g(mlrisc, C.empty) end
1063 :    
1064 :     (* generate code for calls *)
1065 : blume 839 and call(ea, flow, def, use, mem, cutsTo, an, pops) =
1066 : leunga 815 let fun return(set, []) = set
1067 :     | return(set, a::an) =
1068 :     case #peek A.RETURN_ARG a of
1069 :     SOME r => return(C.CellSet.add(r, set), an)
1070 :     | NONE => return(set, an)
1071 : blume 839 in
1072 :     mark(I.CALL{opnd=operand ea,defs=cellset(def),uses=cellset(use),
1073 :     return=return(C.empty,an),cutsTo=cutsTo,mem=mem,
1074 :     pops=pops},an)
1075 : leunga 815 end
1076 : george 545
1077 : leunga 815 (* generate code for integer stores; first move data to %eax
1078 :     * This is mainly because we can't allocate to registers like
1079 :     * ah, dl, dx etc.
1080 :     *)
1081 :     and genStore(mvOp, ea, d, mem, an) =
1082 :     let val src =
1083 : george 545 case immedOrReg(operand d) of
1084 :     src as I.Direct r =>
1085 : leunga 744 if C.sameColor(r,C.eax)
1086 :     then src else (move(src, eax); eax)
1087 : george 545 | src => src
1088 : leunga 815 in mark(I.MOVE{mvOp=mvOp, src=src, dst=address(ea,mem)},an)
1089 : george 545 end
1090 : leunga 815
1091 :     (* generate code for 8-bit integer stores *)
1092 :     (* movb has to use %eax as source. Stupid x86! *)
1093 :     and store8(ea, d, mem, an) = genStore(I.MOVB, ea, d, mem, an)
1094 : blume 818 and store16(ea, d, mem, an) =
1095 :     mark(I.MOVE{mvOp=I.MOVW, src=immedOrReg(operand d), dst=address(ea, mem)}, an)
1096 : george 545 and store32(ea, d, mem, an) =
1097 :     move'(immedOrReg(operand d), address(ea, mem), an)
1098 :    
1099 :     (* generate code for branching *)
1100 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1101 :     (* allow reordering of operands *)
1102 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1103 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1104 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1105 :     fbranch(fty, fcc, t1, t2, lab, an)
1106 :     | branch(ccexp, lab, an) =
1107 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1108 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1109 :     )
1110 :    
1111 :     (* generate code for floating point compare and branch *)
1112 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1113 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1114 :     | ignoreOrder (T.FLOAD _) = true
1115 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1116 :     | ignoreOrder _ = false
1117 :    
1118 :     fun compare'() = (* Sethi-Ullman style *)
1119 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1120 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1121 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1122 :     emit(I.FXCH{opnd=C.ST(1)}));
1123 :     emit(I.FUCOMPP);
1124 :     fcc
1125 :     )
1126 :    
1127 :     fun compare''() =
1128 :     (* direct style *)
1129 :     (* Try to make lsrc the memory operand *)
1130 :     let val lsrc = foperand(fty, t1)
1131 :     val rsrc = foperand(fty, t2)
1132 :     val fsize = fsize fty
1133 :     fun cmp(lsrc, rsrc, fcc) =
1134 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1135 :     in case (lsrc, rsrc) of
1136 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1137 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1138 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1139 :     | (lsrc, rsrc) => (* can't be both memory! *)
1140 :     let val ftmpR = newFreg()
1141 :     val ftmp = I.FPR ftmpR
1142 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1143 :     cmp(lsrc, ftmp, fcc)
1144 :     end
1145 :     end
1146 :    
1147 :     fun compare() =
1148 :     if enableFastFPMode andalso !fast_floating_point
1149 :     then compare''() else compare'()
1150 :    
1151 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1152 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1153 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1154 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1155 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1156 :     fun sahf() = emit(I.SAHF)
1157 : leunga 731 fun branch(fcc) =
1158 : george 545 case fcc
1159 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1160 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1161 :     | T.? => (sahf(); j(I.P,lab))
1162 :     | T.<=> => (sahf(); j(I.NP,lab))
1163 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1164 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1165 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1166 :     | T.?< => (testil 0x500; j(I.NE,lab))
1167 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1168 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1169 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1170 :     cmpil 0x4000; j(I.EQ,lab))
1171 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1172 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1173 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1174 : george 545 | _ => error "fbranch"
1175 :     (*esac*)
1176 : leunga 731 val fcc = compare()
1177 :     in emit I.FNSTSW;
1178 :     branch(fcc)
1179 : monnier 411 end
1180 : monnier 247
1181 : leunga 731 (*========================================================
1182 :     * Floating point code generation starts here.
1183 :     * Some generic fp routines first.
1184 :     *========================================================*)
1185 :    
1186 :     (* Can this tree be folded into the src operand of a floating point
1187 :     * operations?
1188 :     *)
1189 :     and foldableFexp(T.FREG _) = true
1190 :     | foldableFexp(T.FLOAD _) = true
1191 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1192 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1193 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1194 :     | foldableFexp _ = false
1195 :    
1196 :     (* Move integer e of size ty into a memory location.
1197 :     * Returns a quadruple:
1198 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1199 :     *)
1200 :     and convertIntToFloat(ty, e) =
1201 :     let val opnd = operand e
1202 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1203 :     then (INTEGER, ty, opnd, [])
1204 :     else
1205 : leunga 815 let val {instrs, tempMem, cleanup} =
1206 :     cvti2f{ty=ty, src=opnd, an=getAnnotations()}
1207 : leunga 731 in emits instrs;
1208 :     (INTEGER, 32, tempMem, cleanup)
1209 :     end
1210 :     end
1211 :    
1212 :     (*========================================================
1213 :     * Sethi-Ullman based floating point code generation as
1214 :     * implemented by Lal
1215 :     *========================================================*)
1216 :    
1217 : george 545 and fld(32, opnd) = I.FLDS opnd
1218 :     | fld(64, opnd) = I.FLDL opnd
1219 : george 555 | fld(80, opnd) = I.FLDT opnd
1220 : george 545 | fld _ = error "fld"
1221 :    
1222 : leunga 565 and fild(16, opnd) = I.FILD opnd
1223 :     | fild(32, opnd) = I.FILDL opnd
1224 :     | fild(64, opnd) = I.FILDLL opnd
1225 :     | fild _ = error "fild"
1226 :    
1227 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1228 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1229 :    
1230 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1231 :     | fstp(64, opnd) = I.FSTPL opnd
1232 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1233 : george 545 | fstp _ = error "fstp"
1234 :    
1235 :     (* generate code for floating point stores *)
1236 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1237 : george 545 (case d of
1238 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1239 :     | _ => reduceFexp(fty, d, []);
1240 :     mark(fstp(fty, address(ea, mem)), an)
1241 :     )
1242 :    
1243 : leunga 731 (* generate code for floating point loads *)
1244 :     and fload'(fty, ea, mem, fd, an) =
1245 :     let val ea = address(ea, mem)
1246 :     in mark(fld(fty, ea), an);
1247 : leunga 744 if C.sameColor(fd,ST0) then ()
1248 :     else emit(fstp(fty, I.FDirect fd))
1249 : leunga 731 end
1250 :    
1251 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1252 : george 545
1253 :     (* generate floating point expression and put the result in fd *)
1254 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1255 : leunga 744 (if C.sameColor(fs,fd) then ()
1256 : george 545 else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
1257 :     )
1258 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1259 :     fload'(fty, ea, mem, fd, an)
1260 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1261 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1262 : leunga 744 if C.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1263 : leunga 731 )
1264 :     | doFexpr'(fty, e, fd, an) =
1265 : george 545 (reduceFexp(fty, e, []);
1266 : leunga 744 if C.sameColor(fd,ST0) then ()
1267 :     else mark(fstp(fty, I.FDirect fd), an)
1268 : george 545 )
1269 :    
1270 :     (*
1271 :     * Generate floating point expression using Sethi-Ullman's scheme:
1272 :     * This function evaluates a floating point expression,
1273 :     * and put result in %ST(0).
1274 :     *)
1275 :     and reduceFexp(fty, fexp, an) =
1276 : george 555 let val ST = I.ST(C.ST 0)
1277 :     val ST1 = I.ST(C.ST 1)
1278 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1279 : george 545
1280 : leunga 565 datatype su_tree =
1281 :     LEAF of int * T.fexp * ans
1282 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1283 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1284 :     and fbinop = FADD | FSUB | FMUL | FDIV
1285 :     | FIADD | FISUB | FIMUL | FIDIV
1286 :     withtype ans = Annotations.annotations
1287 : monnier 247
1288 : leunga 565 fun label(LEAF(n, _, _)) = n
1289 :     | label(BINARY(n, _, _, _, _, _)) = n
1290 :     | label(UNARY(n, _, _, _, _)) = n
1291 : george 545
1292 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1293 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1294 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1295 : george 545
1296 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1297 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1298 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1299 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1300 :     | su(T.CVTF2F(_, _, t)) = su t
1301 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1302 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1303 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1304 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1305 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1306 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1307 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1308 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1309 :     | su _ = error "su"
1310 :    
1311 :     (* Try to fold the the memory operand or integer conversion *)
1312 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1313 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1314 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1315 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1316 :     | suFold(T.FMARK(t, a)) =
1317 :     let val (t, integer) = suFold t
1318 :     in (annotate(t, a), integer) end
1319 :     | suFold e = (su e, false)
1320 :    
1321 :     (* Form unary tree *)
1322 :     and suUnary(fty, funary, t) =
1323 :     let val t = su t
1324 :     in UNARY(label t, fty, funary, t, [])
1325 : george 545 end
1326 : leunga 565
1327 :     (* Form binary tree *)
1328 :     and suBinary(fty, binop, ibinop, t1, t2) =
1329 :     let val t1 = su t1
1330 :     val (t2, integer) = suFold t2
1331 :     val n1 = label t1
1332 :     val n2 = label t2
1333 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1334 :     val myOp = if integer then ibinop else binop
1335 :     in BINARY(n, fty, myOp, t1, t2, [])
1336 : george 545 end
1337 : george 555
1338 : leunga 565 (* Try to fold in the operand if possible.
1339 :     * This only applies to commutative operations.
1340 :     *)
1341 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1342 : leunga 731 let val (t1, t2) = if foldableFexp t2
1343 :     then (t1, t2) else (t2, t1)
1344 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1345 :    
1346 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1347 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1348 :     t1 = t2 andalso C.sameColor(f1,f2)
1349 : leunga 565 | sameTree _ = false
1350 :    
1351 :     (* Traverse tree and generate code *)
1352 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1353 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1354 :     let val _ = gencode x
1355 :     val (_, fty, src) = leafEA y
1356 :     fun gen(code) = mark(code, a1 @ a2)
1357 :     fun binary(oper32, oper64) =
1358 :     if sameTree(x, t2) then
1359 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1360 : george 555 else
1361 :     let val oper =
1362 : leunga 565 if isMemOpnd src then
1363 :     case fty of
1364 :     32 => oper32
1365 :     | 64 => oper64
1366 :     | _ => error "gencode: BINARY"
1367 :     else oper64
1368 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1369 :     fun ibinary(oper16, oper32) =
1370 :     let val oper = case fty of
1371 :     16 => oper16
1372 :     | 32 => oper32
1373 :     | _ => error "gencode: IBINARY"
1374 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1375 :     in case binop of
1376 :     FADD => binary(I.FADDS, I.FADDL)
1377 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1378 :     | FMUL => binary(I.FMULS, I.FMULL)
1379 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1380 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1381 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1382 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1383 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1384 :     end
1385 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1386 :     let fun doit(t1, t2, oper, operP, operRP) =
1387 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1388 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1389 :     *)
1390 :     val n1 = label t1
1391 :     val n2 = label t2
1392 :     in if n1 < n2 andalso n1 <= 7 then
1393 :     (gencode t2;
1394 :     gencode t1;
1395 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1396 :     else if n2 <= n1 andalso n2 <= 7 then
1397 :     (gencode t1;
1398 :     gencode t2;
1399 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1400 :     else
1401 :     let (* both labels > 7 *)
1402 :     val fs = I.FDirect(newFreg())
1403 :     in gencode t2;
1404 :     emit(fstp(fty, fs));
1405 :     gencode t1;
1406 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1407 :     end
1408 :     end
1409 :     in case binop of
1410 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1411 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1412 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1413 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1414 : george 545 | _ => error "gencode.BINARY"
1415 :     end
1416 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1417 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1418 :    
1419 :     (* Generate code for a leaf.
1420 :     * Returns the type and an effective address
1421 :     *)
1422 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1423 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1424 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1425 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1426 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1427 : leunga 565 | leafEA _ = error "leafEA"
1428 :    
1429 : leunga 731 and int2real(ty, e) =
1430 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1431 :     in cleanupCode := !cleanupCode @ cleanup;
1432 :     (INTEGER, ty, ea)
1433 : george 545 end
1434 : leunga 731
1435 :     in gencode(su fexp);
1436 :     emits(!cleanupCode)
1437 : george 545 end (*reduceFexp*)
1438 : leunga 731
1439 :     (*========================================================
1440 :     * This section generates 3-address style floating
1441 :     * point code.
1442 :     *========================================================*)
1443 :    
1444 :     and isize 16 = I.I16
1445 :     | isize 32 = I.I32
1446 :     | isize _ = error "isize"
1447 :    
1448 :     and fstore''(fty, ea, d, mem, an) =
1449 :     (floatingPointUsed := true;
1450 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1451 :     src=foperand(fty, d)},
1452 :     an)
1453 :     )
1454 :    
1455 :     and fload''(fty, ea, mem, d, an) =
1456 :     (floatingPointUsed := true;
1457 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1458 :     dst=RealReg d}, an)
1459 :     )
1460 :    
1461 :     and fiload''(ity, ea, d, an) =
1462 :     (floatingPointUsed := true;
1463 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1464 :     )
1465 :    
1466 :     and fexpr''(e as T.FREG(_,f)) =
1467 :     if isFMemReg f then transFexpr e else f
1468 :     | fexpr'' e = transFexpr e
1469 :    
1470 :     and transFexpr e =
1471 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1472 :    
1473 :     (*
1474 :     * Process a floating point operand. Put operand in register
1475 :     * when possible. The operand should match the given fty.
1476 :     *)
1477 :     and foperand(fty, e as T.FREG(fty', f)) =
1478 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1479 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1480 :     foperand(fty, e) (* nop on the x86 *)
1481 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1482 :     (* fold operand when the precison matches *)
1483 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1484 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1485 :    
1486 :     (*
1487 :     * Process a floating point operand.
1488 :     * Try to fold in a memory operand or conversion from an integer.
1489 :     *)
1490 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1491 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1492 :     (REAL, fty, address(ea, mem), [])
1493 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1494 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1495 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1496 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1497 :    
1498 :     (* Generate binary operator. Since the real binary operators
1499 :     * does not take memory as destination, we also ensure this
1500 :     * does not happen.
1501 :     *)
1502 :     and fbinop(targetFty,
1503 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1504 :     (* Put the mem operand in rsrc *)
1505 :     let val _ = floatingPointUsed := true;
1506 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1507 :     | isMemOpnd(T.FLOAD _) = true
1508 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1509 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1510 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1511 :     | isMemOpnd _ = false
1512 :     val (binOp, ibinOp, lsrc, rsrc) =
1513 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1514 :     else (binOp, ibinOp, lsrc, rsrc)
1515 :     val lsrc = foperand(targetFty, lsrc)
1516 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1517 :     fun dstMustBeFreg f =
1518 :     if targetFty <> 64 then
1519 :     let val tmpR = newFreg()
1520 :     val tmp = I.FPR tmpR
1521 :     in mark(f tmp, an);
1522 :     emit(I.FMOVE{fsize=fsize targetFty,
1523 :     src=tmp, dst=RealReg fd})
1524 :     end
1525 :     else mark(f(RealReg fd), an)
1526 :     in case kind of
1527 :     REAL =>
1528 :     dstMustBeFreg(fn dst =>
1529 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1530 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1531 :     | INTEGER =>
1532 :     (dstMustBeFreg(fn dst =>
1533 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1534 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1535 :     emits code
1536 :     )
1537 :     end
1538 : george 545
1539 : leunga 731 and funop(fty, unOp, src, fd, an) =
1540 :     let val src = foperand(fty, src)
1541 :     in mark(I.FUNOP{fsize=fsize fty,
1542 :     unOp=unOp, src=src, dst=RealReg fd},an)
1543 :     end
1544 :    
1545 :     and doFexpr''(fty, e, fd, an) =
1546 :     case e of
1547 : leunga 744 T.FREG(_,fs) => if C.sameColor(fs,fd) then ()
1548 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1549 :     (* Stupid x86 does everything as 80-bits internally. *)
1550 :    
1551 :     (* Binary operators *)
1552 :     | T.FADD(_, a, b) => fbinop(fty,
1553 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1554 :     a, b, fd, an)
1555 :     | T.FSUB(_, a, b) => fbinop(fty,
1556 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1557 :     a, b, fd, an)
1558 :     | T.FMUL(_, a, b) => fbinop(fty,
1559 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1560 :     a, b, fd, an)
1561 :     | T.FDIV(_, a, b) => fbinop(fty,
1562 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1563 :     a, b, fd, an)
1564 :    
1565 :     (* Unary operators *)
1566 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1567 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1568 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1569 :    
1570 :     (* Load *)
1571 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1572 :    
1573 :     (* Type conversions *)
1574 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1575 :     | T.CVTI2F(_, ty, e) =>
1576 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1577 :     in fiload''(ty, ea, fd, an);
1578 :     emits cleanup
1579 :     end
1580 :    
1581 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1582 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1583 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1584 :     | T.FEXT fexp =>
1585 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1586 :     | _ => error("doFexpr''")
1587 :    
1588 :     (*========================================================
1589 :     * Tie the two styles of fp code generation together
1590 :     *========================================================*)
1591 :     and fstore(fty, ea, d, mem, an) =
1592 :     if enableFastFPMode andalso !fast_floating_point
1593 :     then fstore''(fty, ea, d, mem, an)
1594 :     else fstore'(fty, ea, d, mem, an)
1595 :     and fload(fty, ea, d, mem, an) =
1596 :     if enableFastFPMode andalso !fast_floating_point
1597 :     then fload''(fty, ea, d, mem, an)
1598 :     else fload'(fty, ea, d, mem, an)
1599 :     and fexpr e =
1600 :     if enableFastFPMode andalso !fast_floating_point
1601 :     then fexpr'' e else fexpr' e
1602 :     and doFexpr(fty, e, fd, an) =
1603 :     if enableFastFPMode andalso !fast_floating_point
1604 :     then doFexpr''(fty, e, fd, an)
1605 :     else doFexpr'(fty, e, fd, an)
1606 :    
1607 : leunga 797 (*================================================================
1608 :     * Optimizations for x := x op y
1609 :     * Special optimizations:
1610 :     * Generate a binary operator, result must in memory.
1611 :     * The source must not be in memory
1612 :     *================================================================*)
1613 :     and binaryMem(binOp, src, dst, mem, an) =
1614 :     mark(I.BINARY{binOp=binOp, src=immedOrReg(operand src),
1615 :     dst=address(dst,mem)}, an)
1616 :     and unaryMem(unOp, opnd, mem, an) =
1617 :     mark(I.UNARY{unOp=unOp, opnd=address(opnd,mem)}, an)
1618 :    
1619 :     and isOne(T.LI n) = n = one
1620 :     | isOne _ = false
1621 :    
1622 :     (*
1623 :     * Perform optimizations based on recognizing
1624 :     * x := x op y or
1625 :     * x := y op x
1626 :     * first.
1627 :     *)
1628 :     and store(ty, ea, d, mem, an,
1629 :     {INC,DEC,ADD,SUB,NOT,NEG,SHL,SHR,SAR,OR,AND,XOR},
1630 :     doStore
1631 :     ) =
1632 :     let fun default() = doStore(ea, d, mem, an)
1633 :     fun binary1(t, t', unary, binary, ea', x) =
1634 :     if t = ty andalso t' = ty then
1635 :     if MLTreeUtils.eqRexp(ea, ea') then
1636 :     if isOne x then unaryMem(unary, ea, mem, an)
1637 :     else binaryMem(binary, x, ea, mem, an)
1638 :     else default()
1639 :     else default()
1640 :     fun unary(t,unOp, ea') =
1641 :     if t = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1642 :     unaryMem(unOp, ea, mem, an)
1643 :     else default()
1644 :     fun binary(t,t',binOp,ea',x) =
1645 :     if t = ty andalso t' = ty andalso
1646 :     MLTreeUtils.eqRexp(ea, ea') then
1647 :     binaryMem(binOp, x, ea, mem, an)
1648 :     else default()
1649 :    
1650 :     fun binaryCom1(t,unOp,binOp,x,y) =
1651 :     if t = ty then
1652 :     let fun again() =
1653 :     case y of
1654 :     T.LOAD(ty',ea',_) =>
1655 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1656 :     if isOne x then unaryMem(unOp, ea, mem, an)
1657 :     else binaryMem(binOp,x,ea,mem,an)
1658 :     else default()
1659 :     | _ => default()
1660 :     in case x of
1661 :     T.LOAD(ty',ea',_) =>
1662 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1663 :     if isOne y then unaryMem(unOp, ea, mem, an)
1664 :     else binaryMem(binOp,y,ea,mem,an)
1665 :     else again()
1666 :     | _ => again()
1667 :     end
1668 :     else default()
1669 :    
1670 :     fun binaryCom(t,binOp,x,y) =
1671 :     if t = ty then
1672 :     let fun again() =
1673 :     case y of
1674 :     T.LOAD(ty',ea',_) =>
1675 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1676 :     binaryMem(binOp,x,ea,mem,an)
1677 :     else default()
1678 :     | _ => default()
1679 :     in case x of
1680 :     T.LOAD(ty',ea',_) =>
1681 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1682 :     binaryMem(binOp,y,ea,mem,an)
1683 :     else again()
1684 :     | _ => again()
1685 :     end
1686 :     else default()
1687 :    
1688 :     in case d of
1689 :     T.ADD(t,x,y) => binaryCom1(t,INC,ADD,x,y)
1690 :     | T.SUB(t,T.LOAD(t',ea',_),x) => binary1(t,t',DEC,SUB,ea',x)
1691 :     | T.ORB(t,x,y) => binaryCom(t,OR,x,y)
1692 :     | T.ANDB(t,x,y) => binaryCom(t,AND,x,y)
1693 :     | T.XORB(t,x,y) => binaryCom(t,XOR,x,y)
1694 :     | T.SLL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHL,ea',x)
1695 :     | T.SRL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHR,ea',x)
1696 :     | T.SRA(t,T.LOAD(t',ea',_),x) => binary(t,t',SAR,ea',x)
1697 :     | T.NEG(t,T.LOAD(t',ea',_)) => unary(t,NEG,ea')
1698 :     | T.NOTB(t,T.LOAD(t',ea',_)) => unary(t,NOT,ea')
1699 :     | _ => default()
1700 :     end (* store *)
1701 :    
1702 : george 545 (* generate code for a statement *)
1703 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1704 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1705 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1706 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1707 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1708 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1709 : blume 839 | stmt(T.CALL{funct, targets, defs, uses, region, pops, ...}, an) =
1710 :     call(funct,targets,defs,uses,region,[],an, pops)
1711 :     | stmt(T.FLOW_TO(T.CALL{funct, targets, defs, uses, region, pops, ...},
1712 : leunga 796 cutTo), an) =
1713 : blume 839 call(funct,targets,defs,uses,region,cutTo,an, pops)
1714 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1715 : leunga 797 | stmt(T.STORE(8, ea, d, mem), an) =
1716 :     store(8, ea, d, mem, an, opcodes8, store8)
1717 :     | stmt(T.STORE(16, ea, d, mem), an) =
1718 :     store(16, ea, d, mem, an, opcodes16, store16)
1719 :     | stmt(T.STORE(32, ea, d, mem), an) =
1720 :     store(32, ea, d, mem, an, opcodes32, store32)
1721 :    
1722 : george 545 | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1723 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1724 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1725 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1726 : george 555 | stmt(T.EXT s, an) =
1727 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1728 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1729 :    
1730 :     and doStmt s = stmt(s, [])
1731 :     and doStmts ss = app doStmt ss
1732 :    
1733 :     and beginCluster' _ =
1734 :     ((* Must be cleared by the client.
1735 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1736 :     *)
1737 : leunga 731 floatingPointUsed := false;
1738 :     trapLabel := NONE;
1739 :     beginCluster 0
1740 :     )
1741 : george 545 and endCluster' a =
1742 : monnier 247 (case !trapLabel
1743 : monnier 411 of NONE => ()
1744 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1745 : monnier 411 (*esac*);
1746 : leunga 731 (* If floating point has been used allocate an extra
1747 :     * register just in case we didn't use any explicit register
1748 :     *)
1749 :     if !floatingPointUsed then (newFreg(); ())
1750 :     else ();
1751 : george 545 endCluster(a)
1752 :     )
1753 :    
1754 :     and reducer() =
1755 :     T.REDUCER{reduceRexp = expr,
1756 :     reduceFexp = fexpr,
1757 :     reduceCCexp = ccExpr,
1758 :     reduceStm = stmt,
1759 :     operand = operand,
1760 :     reduceOperand = reduceOpnd,
1761 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1762 :     emit = mark,
1763 :     instrStream = instrStream,
1764 :     mltreeStream = self()
1765 :     }
1766 :    
1767 :     and self() =
1768 :     S.STREAM
1769 : leunga 815 { beginCluster = beginCluster',
1770 :     endCluster = endCluster',
1771 :     emit = doStmt,
1772 :     pseudoOp = pseudoOp,
1773 :     defineLabel = defineLabel,
1774 :     entryLabel = entryLabel,
1775 :     comment = comment,
1776 :     annotation = annotation,
1777 :     getAnnotations = getAnnotations,
1778 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1779 : george 545 }
1780 :    
1781 :     in self()
1782 : monnier 247 end
1783 :    
1784 : george 545 end (* functor *)
1785 :    
1786 :     end (* local *)

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