Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
ViewVC logotype

Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 984 - (view) (download)

1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 : leunga 797 structure MLTreeUtils : MLTREE_UTILS
43 : george 933 where T = X86Instr.T
44 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
45 : george 933 where I = X86Instr and T = X86Instr.T
46 : george 984 structure MLTreeStream : MLTREE_STREAM
47 :     where T = ExtensionComp.T
48 : george 545 datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
49 :     val arch : arch ref
50 : leunga 593 val cvti2f :
51 : leunga 815 {ty: X86Instr.T.ty,
52 :     src: X86Instr.operand,
53 :     (* source operand, guaranteed to be non-memory! *)
54 :     an: Annotations.annotations ref (* cluster annotations *)
55 :     } ->
56 : leunga 593 {instrs : X86Instr.instruction list,(* the instructions *)
57 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
58 :     cleanup: X86Instr.instruction list (* cleanup code *)
59 :     }
60 : leunga 731 (* When the following flag is set, we allocate floating point registers
61 :     * directly on the floating point stack
62 :     *)
63 :     val fast_floating_point : bool ref
64 : george 545 ) : sig include MLTREECOMP
65 :     val rewriteMemReg : bool
66 :     end =
67 : monnier 247 struct
68 : leunga 775 structure I = X86Instr
69 :     structure T = I.T
70 : george 984 structure TS = ExtensionComp.TS
71 : george 545 structure C = I.C
72 :     structure Shuffle = Shuffle(I)
73 : monnier 247 structure W32 = Word32
74 : george 545 structure A = MLRiscAnnotations
75 : george 909 structure CFG = ExtensionComp.CFG
76 : george 889 structure CB = CellsBasis
77 : monnier 247
78 : george 984 type instrStream = (I.instruction,C.cellset,CFG.cfg) TS.stream
79 :     type mltreeStream = (T.stm,T.mlrisc list,CFG.cfg) TS.stream
80 : leunga 565
81 :     datatype kind = REAL | INTEGER
82 : george 545
83 :     structure Gen = MLTreeGen
84 :     (structure T = T
85 :     val intTy = 32
86 :     val naturalWidths = [32]
87 :     datatype rep = SE | ZE | NEITHER
88 :     val rep = NEITHER
89 :     )
90 :    
91 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
92 : monnier 247
93 : george 545 (* Should we perform automatic MemReg translation?
94 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
95 :     *)
96 :     val rewriteMemReg = rewriteMemReg
97 : leunga 731
98 :     (* The following hardcoded *)
99 : leunga 744 fun isMemReg r = rewriteMemReg andalso
100 : george 889 let val r = CB.registerNum r
101 : leunga 744 in r >= 8 andalso r < 32
102 :     end
103 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
104 : george 889 then let val r = CB.registerNum r
105 : leunga 744 in r >= 8 andalso r < 32 end
106 : leunga 731 else true
107 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
108 : george 889 let val r = CB.registerNum r
109 : leunga 744 in r >= 8 andalso r < 32 end
110 :     )
111 : monnier 247
112 : george 555 val ST0 = C.ST 0
113 :     val ST7 = C.ST 7
114 : leunga 797 val one = T.I.int_1
115 : george 555
116 : leunga 797 val opcodes8 = {INC=I.INCB,DEC=I.DECB,ADD=I.ADDB,SUB=I.SUBB,
117 :     NOT=I.NOTB,NEG=I.NEGB,
118 :     SHL=I.SHLB,SHR=I.SHRB,SAR=I.SARB,
119 :     OR=I.ORB,AND=I.ANDB,XOR=I.XORB}
120 :     val opcodes16 = {INC=I.INCW,DEC=I.DECW,ADD=I.ADDW,SUB=I.SUBW,
121 :     NOT=I.NOTW,NEG=I.NEGW,
122 :     SHL=I.SHLW,SHR=I.SHRW,SAR=I.SARW,
123 :     OR=I.ORW,AND=I.ANDW,XOR=I.XORW}
124 :     val opcodes32 = {INC=I.INCL,DEC=I.DECL,ADD=I.ADDL,SUB=I.SUBL,
125 :     NOT=I.NOTL,NEG=I.NEGL,
126 :     SHL=I.SHLL,SHR=I.SHRL,SAR=I.SARL,
127 :     OR=I.ORL,AND=I.ANDL,XOR=I.XORL}
128 :    
129 : george 545 (*
130 :     * The code generator
131 :     *)
132 : monnier 411 fun selectInstructions
133 : george 545 (instrStream as
134 : george 984 TS.S.STREAM{emit,defineLabel,entryLabel,pseudoOp,annotation,getAnnotations,
135 : leunga 744 beginCluster,endCluster,exitBlock,comment,...}) =
136 : george 545 let exception EA
137 : monnier 411
138 : george 545 (* label where a trap is generated -- one per cluster *)
139 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
140 : monnier 247
141 : leunga 731 (* flag floating point generation *)
142 :     val floatingPointUsed = ref false
143 :    
144 : george 545 (* effective address of an integer register *)
145 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
146 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
147 : monnier 411
148 : george 545 (* Add an overflow trap *)
149 :     fun trap() =
150 :     let val jmp =
151 :     case !trapLabel of
152 : george 909 NONE => let val label = Label.label "trap" ()
153 : george 545 val jmp = I.JCC{cond=I.O,
154 : leunga 775 opnd=I.ImmedLabel(T.LABEL label)}
155 : george 545 in trapLabel := SOME(jmp, label); jmp end
156 :     | SOME(jmp, _) => jmp
157 :     in emit jmp end
158 : monnier 411
159 : george 545 val newReg = C.newReg
160 :     val newFreg = C.newFreg
161 : monnier 247
162 : leunga 731 fun fsize 32 = I.FP32
163 :     | fsize 64 = I.FP64
164 :     | fsize 80 = I.FP80
165 :     | fsize _ = error "fsize"
166 :    
167 : george 545 (* mark an expression with a list of annotations *)
168 :     fun mark'(i,[]) = i
169 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
170 : monnier 247
171 : george 545 (* annotate an expression and emit it *)
172 :     fun mark(i,an) = emit(mark'(i,an))
173 : monnier 247
174 : leunga 731 val emits = app emit
175 :    
176 : george 545 (* emit parallel copies for integers
177 :     * Translates parallel copies that involve memregs into
178 :     * individual copies.
179 :     *)
180 :     fun copy([], [], an) = ()
181 :     | copy(dst, src, an) =
182 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
183 : george 889 if CB.sameColor(rd,rs) then [] else
184 : george 545 let val tmpR = I.Direct(newReg())
185 :     in [I.MOVE{mvOp=I.MOVL, src=src, dst=tmpR},
186 :     I.MOVE{mvOp=I.MOVL, src=tmpR, dst=dst}]
187 :     end
188 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
189 : george 889 if CB.sameColor(rd,rs) then []
190 : george 545 else [I.COPY{dst=[rd], src=[rs], tmp=NONE}]
191 :     | mvInstr{dst, src} = [I.MOVE{mvOp=I.MOVL, src=src, dst=dst}]
192 :     in
193 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
194 : leunga 744 {tmp=SOME(I.Direct(newReg())),
195 : george 545 dst=dst, src=src})
196 :     end
197 :    
198 :     (* conversions *)
199 :     val itow = Word.fromInt
200 :     val wtoi = Word.toInt
201 : george 761 fun toInt32 i = T.I.toInt32(32, i)
202 : george 545 val w32toi32 = Word32.toLargeIntX
203 :     val i32tow32 = Word32.fromLargeInt
204 : monnier 247
205 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
206 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
207 : monnier 247
208 : george 545 (* some useful registers *)
209 :     val eax = I.Direct(C.eax)
210 :     val ecx = I.Direct(C.ecx)
211 :     val edx = I.Direct(C.edx)
212 : monnier 247
213 : leunga 775 fun immedLabel lab = I.ImmedLabel(T.LABEL lab)
214 : george 545
215 :     (* Is the expression zero? *)
216 : george 761 fun isZero(T.LI z) = T.I.isZero z
217 : george 545 | isZero(T.MARK(e,a)) = isZero e
218 :     | isZero _ = false
219 :     (* Does the expression set the zero bit?
220 :     * WARNING: we assume these things are not optimized out!
221 :     *)
222 :     fun setZeroBit(T.ANDB _) = true
223 :     | setZeroBit(T.ORB _) = true
224 :     | setZeroBit(T.XORB _) = true
225 :     | setZeroBit(T.SRA _) = true
226 :     | setZeroBit(T.SRL _) = true
227 :     | setZeroBit(T.SLL _) = true
228 : leunga 695 | setZeroBit(T.SUB _) = true
229 :     | setZeroBit(T.ADDT _) = true
230 :     | setZeroBit(T.SUBT _) = true
231 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
232 :     | setZeroBit _ = false
233 : monnier 247
234 : leunga 695 fun setZeroBit2(T.ANDB _) = true
235 :     | setZeroBit2(T.ORB _) = true
236 :     | setZeroBit2(T.XORB _) = true
237 :     | setZeroBit2(T.SRA _) = true
238 :     | setZeroBit2(T.SRL _) = true
239 :     | setZeroBit2(T.SLL _) = true
240 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
241 :     | setZeroBit2(T.SUB _) = true
242 :     | setZeroBit2(T.ADDT _) = true
243 :     | setZeroBit2(T.SUBT _) = true
244 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
245 :     | setZeroBit2 _ = false
246 :    
247 : leunga 731 (* emit parallel copies for floating point
248 :     * Normal version.
249 :     *)
250 :     fun fcopy'(fty, [], [], _) = ()
251 :     | fcopy'(fty, dst as [_], src as [_], an) =
252 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=NONE}, an)
253 : leunga 731 | fcopy'(fty, dst, src, an) =
254 : george 545 mark(I.FCOPY{dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
255 : monnier 247
256 : leunga 731 (* emit parallel copies for floating point.
257 :     * Fast version.
258 :     * Translates parallel copies that involve memregs into
259 :     * individual copies.
260 :     *)
261 :    
262 :     fun fcopy''(fty, [], [], _) = ()
263 :     | fcopy''(fty, dst, src, an) =
264 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
265 :     let val fsize = fsize fty
266 :     fun mvInstr{dst, src} = [I.FMOVE{fsize=fsize, src=src, dst=dst}]
267 :     in
268 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
269 : leunga 744 {tmp=case dst of
270 : leunga 731 [_] => NONE
271 :     | _ => SOME(I.FPR(newReg())),
272 :     dst=dst, src=src})
273 :     end
274 :     else
275 :     mark(I.FCOPY{dst=dst,src=src,tmp=
276 :     case dst of
277 :     [_] => NONE
278 :     | _ => SOME(I.FPR(newFreg()))}, an)
279 :    
280 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
281 :     then fcopy'' x else fcopy' x
282 :    
283 : george 545 (* Translates MLTREE condition code to x86 condition code *)
284 :     fun cond T.LT = I.LT | cond T.LTU = I.B
285 :     | cond T.LE = I.LE | cond T.LEU = I.BE
286 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
287 :     | cond T.GE = I.GE | cond T.GEU = I.AE
288 :     | cond T.GT = I.GT | cond T.GTU = I.A
289 : monnier 247
290 : leunga 815 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
291 :    
292 : george 545 (* Move and annotate *)
293 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
294 : george 889 if CB.sameColor(s,d) then ()
295 : george 545 else mark(I.COPY{dst=[d], src=[s], tmp=NONE}, an)
296 : leunga 815 | move'(I.Immed 0, dst as I.Direct d, an) =
297 :     mark(I.BINARY{binOp=I.XORL, src=dst, dst=dst}, an)
298 : george 545 | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
299 : monnier 247
300 : george 545 (* Move only! *)
301 :     fun move(src, dst) = move'(src, dst, [])
302 : monnier 247
303 : george 545 val readonly = I.Region.readonly
304 : monnier 247
305 : george 545 (*
306 : george 761 * Compute an effective address.
307 : george 545 *)
308 : george 761 fun address(ea, mem) = let
309 : george 545 (* Keep building a bigger and bigger effective address expressions
310 :     * The input is a list of trees
311 :     * b -- base
312 :     * i -- index
313 :     * s -- scale
314 :     * d -- immed displacement
315 :     *)
316 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
317 :     | doEA(t::trees, b, i, s, d) =
318 :     (case t of
319 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
320 : leunga 775 | T.CONST _ => doEALabel(trees, t, b, i, s, d)
321 :     | T.LABEL _ => doEALabel(trees, t, b, i, s, d)
322 :     | T.LABEXP le => doEALabel(trees, le, b, i, s, d)
323 : george 545 | T.ADD(32, t1, t2 as T.REG(_,r)) =>
324 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
325 :     else doEA(t1::t2::trees, b, i, s, d)
326 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
327 :     | T.SUB(32, t1, T.LI n) =>
328 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
329 :     | T.SLL(32, t1, T.LI n) => let
330 :     val n = T.I.toInt(32, n)
331 :     in
332 :     case n
333 :     of 0 => displace(trees, t1, b, i, s, d)
334 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
335 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
336 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
337 :     | _ => displace(trees, t, b, i, s, d)
338 :     end
339 : george 545 | t => displace(trees, t, b, i, s, d)
340 :     )
341 : monnier 247
342 : george 545 (* Add an immed constant *)
343 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
344 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
345 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
346 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
347 : leunga 775 doEA(trees, b, i, s,
348 :     I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, n)))))
349 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
350 : monnier 247
351 : george 545 (* Add a label expression *)
352 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
353 :     doEA(trees, b, i, s, I.ImmedLabel le)
354 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
355 :     doEA(trees, b, i, s,
356 : leunga 775 I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, m))))
357 : george 545 handle Overflow => error "doEALabel: constant too large")
358 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
359 : leunga 775 doEA(trees, b, i, s, I.ImmedLabel(T.ADD(32,le,le')))
360 : george 545 | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
361 : monnier 247
362 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
363 :     | makeAddressingMode(SOME base, NONE, _, disp) =
364 :     I.Displace{base=base, disp=disp, mem=mem}
365 :     | makeAddressingMode(base, SOME index, scale, disp) =
366 : george 761 I.Indexed{base=base, index=index, scale=scale,
367 : george 545 disp=disp, mem=mem}
368 : monnier 247
369 : george 545 (* generate code for tree and ensure that it is not in %esp *)
370 :     and exprNotEsp tree =
371 :     let val r = expr tree
372 : george 889 in if CB.sameColor(r, C.esp) then
373 : george 545 let val tmp = newReg()
374 :     in move(I.Direct r, I.Direct tmp); tmp end
375 :     else r
376 :     end
377 : monnier 247
378 : george 545 (* Add a base register *)
379 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
380 :     doEA(trees, SOME(expr t), i, s, d)
381 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
382 :     (* make t the index, but make sure that it is not %esp! *)
383 :     let val i = expr t
384 : george 889 in if CB.sameColor(i, C.esp) then
385 : george 545 (* swap base and index *)
386 : george 889 if CB.sameColor(base, C.esp) then
387 : george 545 doEA(trees, SOME i, b, 0, d)
388 :     else (* base and index = %esp! *)
389 :     let val index = newReg()
390 :     in move(I.Direct i, I.Direct index);
391 :     doEA(trees, b, SOME index, 0, d)
392 :     end
393 :     else
394 :     doEA(trees, b, SOME i, 0, d)
395 :     end
396 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
397 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
398 :     in doEA(trees, SOME b, i, s, d) end
399 : monnier 247
400 : george 545 (* Add an indexed register *)
401 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
402 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
403 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
404 :     doEA(trees, SOME(expr t0), i, s, d)
405 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
406 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
407 :     in doEA(trees, SOME b, i, s, d) end
408 :    
409 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
410 :     I.Immed _ => raise EA
411 :     | I.ImmedLabel le => I.LabelEA le
412 :     | ea => ea
413 :     end (* address *)
414 : monnier 247
415 : george 545 (* reduce an expression into an operand *)
416 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
417 : leunga 775 | operand(x as (T.CONST _ | T.LABEL _)) = I.ImmedLabel x
418 :     | operand(T.LABEXP le) = I.ImmedLabel le
419 : george 545 | operand(T.REG(_,r)) = IntReg r
420 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
421 :     | operand(t) = I.Direct(expr t)
422 : monnier 247
423 : george 545 and moveToReg(opnd) =
424 :     let val dst = I.Direct(newReg())
425 :     in move(opnd, dst); dst
426 :     end
427 : monnier 247
428 : george 545 and reduceOpnd(I.Direct r) = r
429 :     | reduceOpnd opnd =
430 :     let val dst = newReg()
431 :     in move(opnd, I.Direct dst); dst
432 :     end
433 : monnier 247
434 : george 545 (* ensure that the operand is either an immed or register *)
435 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
436 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
437 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
438 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
439 :     | immedOrReg opnd = opnd
440 : monnier 247
441 : george 545 and isImmediate(I.Immed _) = true
442 :     | isImmediate(I.ImmedLabel _) = true
443 :     | isImmediate _ = false
444 : monnier 247
445 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
446 :    
447 :     and isMemOpnd opnd =
448 :     (case opnd of
449 :     I.Displace _ => true
450 :     | I.Indexed _ => true
451 :     | I.MemReg _ => true
452 :     | I.LabelEA _ => true
453 : george 555 | I.FDirect f => true
454 : george 545 | _ => false
455 :     )
456 :    
457 :     (*
458 :     * Compute an integer expression and put the result in
459 :     * the destination register rd.
460 :     *)
461 : george 889 and doExpr(exp, rd : CB.cell, an) =
462 : george 545 let val rdOpnd = IntReg rd
463 : monnier 247
464 : george 889 fun equalRd(I.Direct r) = CB.sameColor(r, rd)
465 :     | equalRd(I.MemReg r) = CB.sameColor(r, rd)
466 : george 545 | equalRd _ = false
467 : monnier 247
468 : george 545 (* Emit a binary operator. If the destination is
469 :     * a memReg, do something smarter.
470 :     *)
471 :     fun genBinary(binOp, opnd1, opnd2) =
472 :     if isMemReg rd andalso
473 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
474 :     equalRd(opnd2)
475 :     then
476 :     let val tmpR = newReg()
477 :     val tmp = I.Direct tmpR
478 :     in move(opnd1, tmp);
479 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
480 :     move(tmp, rdOpnd)
481 :     end
482 :     else
483 :     (move(opnd1, rdOpnd);
484 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
485 :     )
486 : monnier 247
487 : george 545 (* Generate a binary operator; it may commute *)
488 :     fun binaryComm(binOp, e1, e2) =
489 :     let val (opnd1, opnd2) =
490 :     case (operand e1, operand e2) of
491 :     (x as I.Immed _, y) => (y, x)
492 :     | (x as I.ImmedLabel _, y) => (y, x)
493 :     | (x, y as I.Direct _) => (y, x)
494 :     | (x, y) => (x, y)
495 :     in genBinary(binOp, opnd1, opnd2)
496 :     end
497 :    
498 :     (* Generate a binary operator; non-commutative *)
499 :     fun binary(binOp, e1, e2) =
500 :     genBinary(binOp, operand e1, operand e2)
501 :    
502 :     (* Generate a unary operator *)
503 :     fun unary(unOp, e) =
504 :     let val opnd = operand e
505 :     in if isMemReg rd andalso isMemOpnd opnd then
506 :     let val tmp = I.Direct(newReg())
507 :     in move(opnd, tmp); move(tmp, rdOpnd)
508 :     end
509 :     else move(opnd, rdOpnd);
510 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
511 :     end
512 :    
513 :     (* Generate shifts; the shift
514 :     * amount must be a constant or in %ecx *)
515 :     fun shift(opcode, e1, e2) =
516 :     let val (opnd1, opnd2) = (operand e1, operand e2)
517 :     in case opnd2 of
518 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
519 :     | _ =>
520 :     if equalRd(opnd2) then
521 :     let val tmpR = newReg()
522 :     val tmp = I.Direct tmpR
523 :     in move(opnd1, tmp);
524 :     move(opnd2, ecx);
525 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
526 :     move(tmp, rdOpnd)
527 :     end
528 :     else
529 :     (move(opnd1, rdOpnd);
530 :     move(opnd2, ecx);
531 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
532 :     )
533 :     end
534 :    
535 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
536 :     fun divrem(signed, overflow, e1, e2, resultReg) =
537 :     let val (opnd1, opnd2) = (operand e1, operand e2)
538 :     val _ = move(opnd1, eax)
539 : leunga 815 val oper = if signed then (emit(I.CDQ); I.IDIVL1)
540 :     else (zero edx; I.DIVL1)
541 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
542 :     move(resultReg, rdOpnd);
543 :     if overflow then trap() else ()
544 :     end
545 :    
546 :     (* Optimize the special case for division *)
547 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
548 :     val n = toInt32 n'
549 :     val w = T.I.toWord32(32, n')
550 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
551 : george 545 fun log2 n = (* n must be > 0!!! *)
552 :     let fun loop(0w1,pow) = pow
553 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
554 : george 545 in loop(n,0) end
555 :     in if n > 1 andalso isPowerOf2 w then
556 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
557 : george 545 in if signed then
558 :     (* signed; simulate round towards zero *)
559 : george 909 let val label = Label.anon()
560 : george 545 val reg1 = expr e1
561 :     val opnd1 = I.Direct reg1
562 :     in if setZeroBit e1 then ()
563 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
564 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
565 :     emit(if n = 2 then
566 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
567 :     else
568 :     I.BINARY{binOp=I.ADDL,
569 : george 761 src=I.Immed(n - 1),
570 : george 545 dst=opnd1});
571 :     defineLabel label;
572 :     shift(I.SARL, T.REG(32, reg1), pow)
573 :     end
574 :     else (* unsigned *)
575 :     shift(I.SHRL, e1, pow)
576 :     end
577 :     else
578 :     (* note the only way we can overflow is if
579 :     * n = 0 or n = -1
580 :     *)
581 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
582 :     e1, e2, eax)
583 :     end
584 :     | divide(signed, overflow, e1, e2) =
585 :     divrem(signed, overflow, e1, e2, eax)
586 : monnier 247
587 : george 545 fun rem(signed, overflow, e1, e2) =
588 :     divrem(signed, overflow, e1, e2, edx)
589 : leunga 815
590 :     (* Makes sure the destination must be a register *)
591 :     fun dstMustBeReg f =
592 :     if isMemReg rd then
593 :     let val tmpR = newReg()
594 :     val tmp = I.Direct(tmpR)
595 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
596 :     else f(rd, rdOpnd)
597 :    
598 : george 545 (* unsigned integer multiplication *)
599 :     fun uMultiply(e1, e2) =
600 :     (* note e2 can never be (I.Direct edx) *)
601 :     (move(operand e1, eax);
602 : leunga 815 mark(I.MULTDIV{multDivOp=I.MULL1,
603 : george 545 src=regOrMem(operand e2)},an);
604 :     move(eax, rdOpnd)
605 :     )
606 :    
607 :     (* signed integer multiplication:
608 :     * The only forms that are allowed that also sets the
609 :     * OF and CF flags are:
610 :     *
611 : leunga 815 * (dst) (src1) (src2)
612 : george 545 * imul r32, r32/m32, imm8
613 : leunga 815 * (dst) (src)
614 : george 545 * imul r32, imm8
615 :     * imul r32, imm32
616 : leunga 815 * imul r32, r32/m32
617 :     * Note: destination must be a register!
618 : george 545 *)
619 :     fun multiply(e1, e2) =
620 : leunga 815 dstMustBeReg(fn (rd, rdOpnd) =>
621 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _) =
622 :     (move(i1, rdOpnd);
623 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=i2},an))
624 :     | doit(rm, i2 as I.Immed _) = doit(i2, rm)
625 :     | doit(imm as I.Immed(i), rm) =
626 :     mark(I.MUL3{dst=rd, src1=rm, src2=i},an)
627 :     | doit(r1 as I.Direct _, r2 as I.Direct _) =
628 :     (move(r1, rdOpnd);
629 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=r2},an))
630 :     | doit(r1 as I.Direct _, rm) =
631 :     (move(r1, rdOpnd);
632 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm},an))
633 :     | doit(rm, r as I.Direct _) = doit(r, rm)
634 :     | doit(rm1, rm2) =
635 : george 545 if equalRd rm2 then
636 :     let val tmpR = newReg()
637 :     val tmp = I.Direct tmpR
638 :     in move(rm1, tmp);
639 : leunga 815 mark(I.BINARY{binOp=I.IMULL, dst=tmp, src=rm2},an);
640 :     move(tmp, rdOpnd)
641 : george 545 end
642 :     else
643 : leunga 815 (move(rm1, rdOpnd);
644 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm2},an)
645 : george 545 )
646 :     val (opnd1, opnd2) = (operand e1, operand e2)
647 : leunga 815 in doit(opnd1, opnd2)
648 : george 545 end
649 : leunga 815 )
650 : monnier 247
651 : george 545 (* Emit a load instruction; makes sure that the destination
652 :     * is a register
653 :     *)
654 :     fun genLoad(mvOp, ea, mem) =
655 :     dstMustBeReg(fn (_, dst) =>
656 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
657 :    
658 :     (* Generate a zero extended loads *)
659 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
660 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
661 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
662 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
663 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
664 :    
665 :     (* Generate a sign extended loads *)
666 :    
667 :     (* Generate setcc instruction:
668 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
669 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
670 :     * Note that we have to use eax as the destination of the
671 :     * setcc because it only works on the registers
672 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
673 :     * are inaccessible in 32 bit mode.
674 : george 545 *)
675 :     fun setcc(ty, cc, t1, t2, yes, no) =
676 : leunga 583 let val (cc, yes, no) =
677 :     if yes > no then (cc, yes, no)
678 :     else (T.Basis.negateCond cc, no, yes)
679 : george 545 in (* Clear the destination first.
680 :     * This this because stupid SETcc
681 :     * only writes to the low order
682 :     * byte. That's Intel architecture, folks.
683 :     *)
684 : leunga 695 case (yes, no, cc) of
685 :     (1, 0, T.LT) =>
686 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
687 :     in move(tmp, rdOpnd);
688 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
689 :     end
690 :     | (1, 0, T.GT) =>
691 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
692 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
693 :     move(tmp, rdOpnd);
694 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
695 :     end
696 :     | (1, 0, _) => (* normal case *)
697 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
698 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
699 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
700 : leunga 583 move(eax, rdOpnd)
701 :     end
702 : leunga 695 | (C1, C2, _) =>
703 : george 545 (* general case;
704 : leunga 583 * from the Intel optimization guide p3-5
705 :     *)
706 : leunga 695 let val _ = zero eax;
707 :     val cc = cmp(true, ty, cc, t1, t2, [])
708 : leunga 583 in case C1-C2 of
709 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
710 :     let val (base,scale) =
711 :     case D of
712 :     1 => (NONE, 0)
713 :     | 2 => (NONE, 1)
714 :     | 3 => (SOME C.eax, 1)
715 :     | 4 => (NONE, 2)
716 :     | 5 => (SOME C.eax, 2)
717 :     | 8 => (NONE, 3)
718 :     | 9 => (SOME C.eax, 3)
719 :     val addr = I.Indexed{base=base,
720 :     index=C.eax,
721 :     scale=scale,
722 :     disp=I.Immed C2,
723 : george 545 mem=readonly}
724 : leunga 583 val tmpR = newReg()
725 :     val tmp = I.Direct tmpR
726 :     in emit(I.SET{cond=cond cc, opnd=eax});
727 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
728 :     move(tmp, rdOpnd)
729 :     end
730 :     | D =>
731 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
732 :     opnd=eax});
733 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
734 :     emit(I.BINARY{binOp=I.ANDL,
735 :     src=I.Immed D, dst=eax});
736 :     if C2 = 0 then
737 :     move(eax, rdOpnd)
738 :     else
739 :     let val tmpR = newReg()
740 :     val tmp = I.Direct tmpR
741 :     in mark(I.LEA{addr=
742 :     I.Displace{
743 :     base=C.eax,
744 :     disp=I.Immed C2,
745 :     mem=readonly},
746 :     r32=tmpR}, an);
747 :     move(tmp, rdOpnd)
748 :     end
749 :     )
750 :     end
751 : george 545 end (* setcc *)
752 :    
753 :     (* Generate cmovcc instruction.
754 :     * on Pentium Pro and Pentium II only
755 :     *)
756 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
757 :     let fun genCmov(dstR, _) =
758 :     let val _ = doExpr(no, dstR, []) (* false branch *)
759 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
760 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
761 :     end
762 :     in dstMustBeReg genCmov
763 :     end
764 :    
765 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
766 : monnier 247
767 : leunga 606 (* Add n to rd *)
768 :     fun addN n =
769 :     let val n = operand n
770 :     val src = if isMemReg rd then immedOrReg n else n
771 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
772 :    
773 : george 545 (* Generate addition *)
774 :     fun addition(e1, e2) =
775 : leunga 606 case e1 of
776 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e2
777 : leunga 744 else addition1(e1,e2)
778 : leunga 606 | _ => addition1(e1,e2)
779 :     and addition1(e1, e2) =
780 :     case e2 of
781 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e1
782 : leunga 744 else addition2(e1,e2)
783 : leunga 606 | _ => addition2(e1,e2)
784 :     and addition2(e1,e2) =
785 : george 545 (dstMustBeReg(fn (dstR, _) =>
786 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
787 :     handle EA => binaryComm(I.ADDL, e1, e2))
788 : monnier 247
789 :    
790 : george 545 in case exp of
791 :     T.REG(_,rs) =>
792 :     if isMemReg rs andalso isMemReg rd then
793 :     let val tmp = I.Direct(newReg())
794 : leunga 731 in move'(I.MemReg rs, tmp, an);
795 : george 545 move'(tmp, rdOpnd, [])
796 :     end
797 :     else move'(IntReg rs, rdOpnd, an)
798 : george 761 | T.LI z => let
799 :     val n = toInt32 z
800 :     in
801 :     if n=0 then
802 :     (* As per Fermin's request, special optimization for rd := 0.
803 :     * Currently we don't bother with the size.
804 :     *)
805 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
806 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
807 :     else
808 :     move'(I.Immed(n), rdOpnd, an)
809 :     end
810 : leunga 775 | (T.CONST _ | T.LABEL _) =>
811 :     move'(I.ImmedLabel exp, rdOpnd, an)
812 :     | T.LABEXP le => move'(I.ImmedLabel le, rdOpnd, an)
813 : monnier 247
814 : george 545 (* 32-bit addition *)
815 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
816 :     val n = toInt32 n
817 :     in
818 :     case n
819 :     of 1 => unary(I.INCL, e1)
820 :     | ~1 => unary(I.DECL, e1)
821 :     | _ => addition(e1, e2)
822 :     end
823 :     | T.ADD(32, e1 as T.LI n, e2) => let
824 :     val n = toInt32 n
825 :     in
826 :     case n
827 :     of 1 => unary(I.INCL, e2)
828 :     | ~1 => unary(I.DECL, e2)
829 :     | _ => addition(e1, e2)
830 :     end
831 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
832 : monnier 247
833 : leunga 695 (* 32-bit addition but set the flag!
834 :     * This is a stupid hack for now.
835 :     *)
836 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
837 :     val n = T.I.toInt(32, n)
838 :     in
839 :     if n=1 then unary(I.INCL, e)
840 :     else if n = ~1 then unary(I.DECL, e)
841 :     else binaryComm(I.ADDL, e, e1)
842 :     end
843 :     | T.ADD(0, e1 as T.LI n, e) => let
844 :     val n = T.I.toInt(32, n)
845 :     in
846 :     if n=1 then unary(I.INCL, e)
847 :     else if n = ~1 then unary(I.DECL, e)
848 :     else binaryComm(I.ADDL, e1, e)
849 :     end
850 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
851 :    
852 : george 545 (* 32-bit subtraction *)
853 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
854 :     val n = toInt32 n
855 :     in
856 :     case n
857 :     of 0 => doExpr(e1, rd, an)
858 :     | 1 => unary(I.DECL, e1)
859 :     | ~1 => unary(I.INCL, e1)
860 :     | _ => binary(I.SUBL, e1, e2)
861 :     end
862 :     | T.SUB(32, e1 as T.LI n, e2) =>
863 :     if T.I.isZero n then unary(I.NEGL, e2)
864 :     else binary(I.SUBL, e1, e2)
865 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
866 : monnier 247
867 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
868 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
869 :     | T.REMU(32, x, y) => rem(false, false, x, y)
870 : monnier 247
871 : george 545 | T.MULS(32, x, y) => multiply(x, y)
872 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
873 :     | T.REMS(32, x, y) => rem(true, false, x, y)
874 : monnier 247
875 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
876 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
877 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
878 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
879 :     | T.REMT(32, x, y) => rem(true, true, x, y)
880 : monnier 247
881 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
882 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
883 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
884 :     | T.NOTB(32, x) => unary(I.NOTL, x)
885 : monnier 247
886 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
887 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
888 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
889 : monnier 247
890 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
891 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
892 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
893 : monnier 498
894 : leunga 776 | T.SX(32,8,T.LOAD(8,ea,mem)) => load8s(ea, mem)
895 :     | T.SX(32,16,T.LOAD(16,ea,mem)) => load16s(ea, mem)
896 :     | T.ZX(32,8,T.LOAD(8,ea,mem)) => load8(ea, mem)
897 : leunga 779 | T.ZX(32,16,T.LOAD(16,ea,mem)) => load16(ea, mem)
898 : leunga 776
899 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
900 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
901 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
902 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
903 :     Pentium => unknownExp exp
904 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
905 :     )
906 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
907 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
908 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
909 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
910 : george 555 | T.REXT e =>
911 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
912 : george 545 (* simplify and try again *)
913 :     | exp => unknownExp exp
914 :     end (* doExpr *)
915 : monnier 247
916 : george 545 (* generate an expression and return its result register
917 :     * If rewritePseudo is on, the result is guaranteed to be in a
918 :     * non memReg register
919 :     *)
920 :     and expr(exp as T.REG(_, rd)) =
921 :     if isMemReg rd then genExpr exp else rd
922 :     | expr exp = genExpr exp
923 : monnier 247
924 : george 545 and genExpr exp =
925 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
926 : monnier 247
927 : george 545 (* Compare an expression with zero.
928 :     * On the x86, TEST is superior to AND for doing the same thing,
929 :     * since it doesn't need to write out the result in a register.
930 :     *)
931 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
932 : george 545 (case ty of
933 : leunga 695 8 => test(I.TESTB, a, b, an)
934 :     | 16 => test(I.TESTW, a, b, an)
935 :     | 32 => test(I.TESTL, a, b, an)
936 :     | _ => doExpr(e, newReg(), an);
937 :     cc)
938 :     | cmpWithZero(cc, e, an) =
939 :     let val e =
940 :     case e of (* hack to disable the lea optimization XXX *)
941 :     T.ADD(_, a, b) => T.ADD(0, a, b)
942 :     | e => e
943 :     in doExpr(e, newReg(), an); cc end
944 : monnier 247
945 : george 545 (* Emit a test.
946 :     * The available modes are
947 :     * r/m, r
948 :     * r/m, imm
949 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
950 :     * When anding an operand with a constant
951 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
952 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
953 :     * this works for memory operands too. However, with TESTB, it is
954 :     * not possible to use registers other than
955 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
956 :     * perform register allocation first, and if the operand registers
957 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
958 :     * by TESTB.
959 :     *)
960 : leunga 695 and test(testopcode, a, b, an) =
961 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
962 :     (* translate r, r/m => r/m, r *)
963 :     val (opnd1, opnd2) =
964 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
965 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
966 : george 545 end
967 : monnier 247
968 : leunga 815 (* %eflags <- src *)
969 :     and moveToEflags src =
970 : george 889 if CB.sameColor(src, C.eflags) then ()
971 : leunga 815 else (move(I.Direct src, eax); emit(I.LAHF))
972 :    
973 :     (* dst <- %eflags *)
974 :     and moveFromEflags dst =
975 : george 889 if CB.sameColor(dst, C.eflags) then ()
976 : leunga 815 else (emit(I.SAHF); move(eax, I.Direct dst))
977 :    
978 : george 545 (* generate a condition code expression
979 : leunga 744 * The zero is for setting the condition code!
980 :     * I have no idea why this is used.
981 :     *)
982 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
983 : leunga 815 (cmp(false, ty, cc, t1, t2, an);
984 :     moveFromEflags rd
985 :     )
986 :     | doCCexpr(T.CC(cond,rs), rd, an) =
987 : george 889 if CB.sameColor(rs,C.eflags) orelse CB.sameColor(rd,C.eflags) then
988 : leunga 815 (moveToEflags rs; moveFromEflags rd)
989 : leunga 744 else
990 : leunga 815 move'(I.Direct rs, I.Direct rd, an)
991 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
992 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
993 :     | doCCexpr(T.CCEXT e, cd, an) =
994 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
995 : george 545 | doCCexpr _ = error "doCCexpr"
996 : monnier 247
997 : george 545 and ccExpr e = error "ccExpr"
998 : monnier 247
999 : george 545 (* generate a comparison and sets the condition code;
1000 :     * return the actual cc used. If the flag swapable is true,
1001 :     * we can also reorder the operands.
1002 :     *)
1003 :     and cmp(swapable, ty, cc, t1, t2, an) =
1004 : leunga 695 (* == and <> can be always be reordered *)
1005 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
1006 :     in (* Sometimes the comparison is not necessary because
1007 :     * the bits are already set!
1008 :     *)
1009 :     if isZero t1 andalso setZeroBit2 t2 then
1010 :     if swapable then
1011 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
1012 :     else (* can't reorder the comparison! *)
1013 :     genCmp(ty, false, cc, t1, t2, an)
1014 :     else if isZero t2 andalso setZeroBit2 t1 then
1015 :     cmpWithZero(cc, t1, an)
1016 :     else genCmp(ty, swapable, cc, t1, t2, an)
1017 :     end
1018 : monnier 247
1019 : george 545 (* Give a and b which are the operands to a comparison (or test)
1020 :     * Return the appropriate condition code and operands.
1021 :     * The available modes are:
1022 :     * r/m, imm
1023 :     * r/m, r
1024 :     * r, r/m
1025 :     *)
1026 :     and commuteComparison(cc, swapable, a, b) =
1027 :     let val (opnd1, opnd2) = (operand a, operand b)
1028 :     in (* Try to fold in the operands whenever possible *)
1029 :     case (isImmediate opnd1, isImmediate opnd2) of
1030 :     (true, true) => (cc, moveToReg opnd1, opnd2)
1031 :     | (true, false) =>
1032 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
1033 :     else (cc, moveToReg opnd1, opnd2)
1034 :     | (false, true) => (cc, opnd1, opnd2)
1035 :     | (false, false) =>
1036 :     (case (opnd1, opnd2) of
1037 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1038 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1039 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1040 :     )
1041 :     end
1042 :    
1043 :     (* generate a real comparison; return the real cc used *)
1044 :     and genCmp(ty, swapable, cc, a, b, an) =
1045 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1046 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1047 :     end
1048 : monnier 247
1049 : george 545 (* generate code for jumps *)
1050 : leunga 775 and jmp(lexp as T.LABEL lab, labs, an) =
1051 : george 545 mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1052 : leunga 775 | jmp(T.LABEXP le, labs, an) = mark(I.JMP(I.ImmedLabel le, labs), an)
1053 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1054 : george 545
1055 :     (* convert mlrisc to cellset:
1056 :     *)
1057 :     and cellset mlrisc =
1058 : jhr 900 let val addCCReg = CB.CellSet.add
1059 : george 545 fun g([],acc) = acc
1060 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1061 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1062 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1063 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1064 :     | g(_::regs, acc) = g(regs, acc)
1065 :     in g(mlrisc, C.empty) end
1066 :    
1067 :     (* generate code for calls *)
1068 : blume 839 and call(ea, flow, def, use, mem, cutsTo, an, pops) =
1069 : leunga 815 let fun return(set, []) = set
1070 :     | return(set, a::an) =
1071 :     case #peek A.RETURN_ARG a of
1072 : jhr 900 SOME r => return(CB.CellSet.add(r, set), an)
1073 : leunga 815 | NONE => return(set, an)
1074 : blume 839 in
1075 :     mark(I.CALL{opnd=operand ea,defs=cellset(def),uses=cellset(use),
1076 :     return=return(C.empty,an),cutsTo=cutsTo,mem=mem,
1077 :     pops=pops},an)
1078 : leunga 815 end
1079 : george 545
1080 : leunga 815 (* generate code for integer stores; first move data to %eax
1081 :     * This is mainly because we can't allocate to registers like
1082 :     * ah, dl, dx etc.
1083 :     *)
1084 :     and genStore(mvOp, ea, d, mem, an) =
1085 :     let val src =
1086 : george 545 case immedOrReg(operand d) of
1087 :     src as I.Direct r =>
1088 : george 889 if CB.sameColor(r,C.eax)
1089 : leunga 744 then src else (move(src, eax); eax)
1090 : george 545 | src => src
1091 : leunga 815 in mark(I.MOVE{mvOp=mvOp, src=src, dst=address(ea,mem)},an)
1092 : george 545 end
1093 : leunga 815
1094 :     (* generate code for 8-bit integer stores *)
1095 :     (* movb has to use %eax as source. Stupid x86! *)
1096 :     and store8(ea, d, mem, an) = genStore(I.MOVB, ea, d, mem, an)
1097 : blume 818 and store16(ea, d, mem, an) =
1098 :     mark(I.MOVE{mvOp=I.MOVW, src=immedOrReg(operand d), dst=address(ea, mem)}, an)
1099 : george 545 and store32(ea, d, mem, an) =
1100 :     move'(immedOrReg(operand d), address(ea, mem), an)
1101 :    
1102 :     (* generate code for branching *)
1103 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1104 :     (* allow reordering of operands *)
1105 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1106 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1107 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1108 :     fbranch(fty, fcc, t1, t2, lab, an)
1109 :     | branch(ccexp, lab, an) =
1110 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1111 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1112 :     )
1113 :    
1114 :     (* generate code for floating point compare and branch *)
1115 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1116 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1117 :     | ignoreOrder (T.FLOAD _) = true
1118 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1119 :     | ignoreOrder _ = false
1120 :    
1121 :     fun compare'() = (* Sethi-Ullman style *)
1122 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1123 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1124 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1125 :     emit(I.FXCH{opnd=C.ST(1)}));
1126 :     emit(I.FUCOMPP);
1127 :     fcc
1128 :     )
1129 :    
1130 :     fun compare''() =
1131 :     (* direct style *)
1132 :     (* Try to make lsrc the memory operand *)
1133 :     let val lsrc = foperand(fty, t1)
1134 :     val rsrc = foperand(fty, t2)
1135 :     val fsize = fsize fty
1136 :     fun cmp(lsrc, rsrc, fcc) =
1137 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1138 :     in case (lsrc, rsrc) of
1139 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1140 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1141 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1142 :     | (lsrc, rsrc) => (* can't be both memory! *)
1143 :     let val ftmpR = newFreg()
1144 :     val ftmp = I.FPR ftmpR
1145 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1146 :     cmp(lsrc, ftmp, fcc)
1147 :     end
1148 :     end
1149 :    
1150 :     fun compare() =
1151 :     if enableFastFPMode andalso !fast_floating_point
1152 :     then compare''() else compare'()
1153 :    
1154 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1155 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1156 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1157 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1158 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1159 :     fun sahf() = emit(I.SAHF)
1160 : leunga 731 fun branch(fcc) =
1161 : george 545 case fcc
1162 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1163 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1164 :     | T.? => (sahf(); j(I.P,lab))
1165 :     | T.<=> => (sahf(); j(I.NP,lab))
1166 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1167 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1168 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1169 :     | T.?< => (testil 0x500; j(I.NE,lab))
1170 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1171 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1172 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1173 :     cmpil 0x4000; j(I.EQ,lab))
1174 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1175 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1176 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1177 : george 545 | _ => error "fbranch"
1178 :     (*esac*)
1179 : leunga 731 val fcc = compare()
1180 :     in emit I.FNSTSW;
1181 :     branch(fcc)
1182 : monnier 411 end
1183 : monnier 247
1184 : leunga 731 (*========================================================
1185 :     * Floating point code generation starts here.
1186 :     * Some generic fp routines first.
1187 :     *========================================================*)
1188 :    
1189 :     (* Can this tree be folded into the src operand of a floating point
1190 :     * operations?
1191 :     *)
1192 :     and foldableFexp(T.FREG _) = true
1193 :     | foldableFexp(T.FLOAD _) = true
1194 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1195 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1196 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1197 :     | foldableFexp _ = false
1198 :    
1199 :     (* Move integer e of size ty into a memory location.
1200 :     * Returns a quadruple:
1201 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1202 :     *)
1203 :     and convertIntToFloat(ty, e) =
1204 :     let val opnd = operand e
1205 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1206 :     then (INTEGER, ty, opnd, [])
1207 :     else
1208 : leunga 815 let val {instrs, tempMem, cleanup} =
1209 :     cvti2f{ty=ty, src=opnd, an=getAnnotations()}
1210 : leunga 731 in emits instrs;
1211 :     (INTEGER, 32, tempMem, cleanup)
1212 :     end
1213 :     end
1214 :    
1215 :     (*========================================================
1216 :     * Sethi-Ullman based floating point code generation as
1217 :     * implemented by Lal
1218 :     *========================================================*)
1219 :    
1220 : george 545 and fld(32, opnd) = I.FLDS opnd
1221 :     | fld(64, opnd) = I.FLDL opnd
1222 : george 555 | fld(80, opnd) = I.FLDT opnd
1223 : george 545 | fld _ = error "fld"
1224 :    
1225 : leunga 565 and fild(16, opnd) = I.FILD opnd
1226 :     | fild(32, opnd) = I.FILDL opnd
1227 :     | fild(64, opnd) = I.FILDLL opnd
1228 :     | fild _ = error "fild"
1229 :    
1230 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1231 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1232 :    
1233 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1234 :     | fstp(64, opnd) = I.FSTPL opnd
1235 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1236 : george 545 | fstp _ = error "fstp"
1237 :    
1238 :     (* generate code for floating point stores *)
1239 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1240 : george 545 (case d of
1241 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1242 :     | _ => reduceFexp(fty, d, []);
1243 :     mark(fstp(fty, address(ea, mem)), an)
1244 :     )
1245 :    
1246 : leunga 731 (* generate code for floating point loads *)
1247 :     and fload'(fty, ea, mem, fd, an) =
1248 :     let val ea = address(ea, mem)
1249 :     in mark(fld(fty, ea), an);
1250 : george 889 if CB.sameColor(fd,ST0) then ()
1251 : leunga 744 else emit(fstp(fty, I.FDirect fd))
1252 : leunga 731 end
1253 :    
1254 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1255 : george 545
1256 :     (* generate floating point expression and put the result in fd *)
1257 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1258 : george 889 (if CB.sameColor(fs,fd) then ()
1259 : george 545 else mark(I.FCOPY{dst=[fd], src=[fs], tmp=NONE}, an)
1260 :     )
1261 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1262 :     fload'(fty, ea, mem, fd, an)
1263 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1264 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1265 : george 889 if CB.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1266 : leunga 731 )
1267 :     | doFexpr'(fty, e, fd, an) =
1268 : george 545 (reduceFexp(fty, e, []);
1269 : george 889 if CB.sameColor(fd,ST0) then ()
1270 : leunga 744 else mark(fstp(fty, I.FDirect fd), an)
1271 : george 545 )
1272 :    
1273 :     (*
1274 :     * Generate floating point expression using Sethi-Ullman's scheme:
1275 :     * This function evaluates a floating point expression,
1276 :     * and put result in %ST(0).
1277 :     *)
1278 :     and reduceFexp(fty, fexp, an) =
1279 : george 555 let val ST = I.ST(C.ST 0)
1280 :     val ST1 = I.ST(C.ST 1)
1281 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1282 : george 545
1283 : leunga 565 datatype su_tree =
1284 :     LEAF of int * T.fexp * ans
1285 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1286 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1287 :     and fbinop = FADD | FSUB | FMUL | FDIV
1288 :     | FIADD | FISUB | FIMUL | FIDIV
1289 :     withtype ans = Annotations.annotations
1290 : monnier 247
1291 : leunga 565 fun label(LEAF(n, _, _)) = n
1292 :     | label(BINARY(n, _, _, _, _, _)) = n
1293 :     | label(UNARY(n, _, _, _, _)) = n
1294 : george 545
1295 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1296 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1297 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1298 : george 545
1299 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1300 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1301 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1302 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1303 :     | su(T.CVTF2F(_, _, t)) = su t
1304 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1305 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1306 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1307 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1308 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1309 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1310 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1311 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1312 :     | su _ = error "su"
1313 :    
1314 :     (* Try to fold the the memory operand or integer conversion *)
1315 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1316 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1317 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1318 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1319 :     | suFold(T.FMARK(t, a)) =
1320 :     let val (t, integer) = suFold t
1321 :     in (annotate(t, a), integer) end
1322 :     | suFold e = (su e, false)
1323 :    
1324 :     (* Form unary tree *)
1325 :     and suUnary(fty, funary, t) =
1326 :     let val t = su t
1327 :     in UNARY(label t, fty, funary, t, [])
1328 : george 545 end
1329 : leunga 565
1330 :     (* Form binary tree *)
1331 :     and suBinary(fty, binop, ibinop, t1, t2) =
1332 :     let val t1 = su t1
1333 :     val (t2, integer) = suFold t2
1334 :     val n1 = label t1
1335 :     val n2 = label t2
1336 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1337 :     val myOp = if integer then ibinop else binop
1338 :     in BINARY(n, fty, myOp, t1, t2, [])
1339 : george 545 end
1340 : george 555
1341 : leunga 565 (* Try to fold in the operand if possible.
1342 :     * This only applies to commutative operations.
1343 :     *)
1344 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1345 : leunga 731 let val (t1, t2) = if foldableFexp t2
1346 :     then (t1, t2) else (t2, t1)
1347 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1348 :    
1349 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1350 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1351 : george 889 t1 = t2 andalso CB.sameColor(f1,f2)
1352 : leunga 565 | sameTree _ = false
1353 :    
1354 :     (* Traverse tree and generate code *)
1355 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1356 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1357 :     let val _ = gencode x
1358 :     val (_, fty, src) = leafEA y
1359 :     fun gen(code) = mark(code, a1 @ a2)
1360 :     fun binary(oper32, oper64) =
1361 :     if sameTree(x, t2) then
1362 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1363 : george 555 else
1364 :     let val oper =
1365 : leunga 565 if isMemOpnd src then
1366 :     case fty of
1367 :     32 => oper32
1368 :     | 64 => oper64
1369 :     | _ => error "gencode: BINARY"
1370 :     else oper64
1371 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1372 :     fun ibinary(oper16, oper32) =
1373 :     let val oper = case fty of
1374 :     16 => oper16
1375 :     | 32 => oper32
1376 :     | _ => error "gencode: IBINARY"
1377 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1378 :     in case binop of
1379 :     FADD => binary(I.FADDS, I.FADDL)
1380 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1381 :     | FMUL => binary(I.FMULS, I.FMULL)
1382 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1383 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1384 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1385 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1386 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1387 :     end
1388 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1389 :     let fun doit(t1, t2, oper, operP, operRP) =
1390 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1391 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1392 :     *)
1393 :     val n1 = label t1
1394 :     val n2 = label t2
1395 :     in if n1 < n2 andalso n1 <= 7 then
1396 :     (gencode t2;
1397 :     gencode t1;
1398 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1399 :     else if n2 <= n1 andalso n2 <= 7 then
1400 :     (gencode t1;
1401 :     gencode t2;
1402 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1403 :     else
1404 :     let (* both labels > 7 *)
1405 :     val fs = I.FDirect(newFreg())
1406 :     in gencode t2;
1407 :     emit(fstp(fty, fs));
1408 :     gencode t1;
1409 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1410 :     end
1411 :     end
1412 :     in case binop of
1413 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1414 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1415 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1416 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1417 : george 545 | _ => error "gencode.BINARY"
1418 :     end
1419 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1420 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1421 :    
1422 :     (* Generate code for a leaf.
1423 :     * Returns the type and an effective address
1424 :     *)
1425 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1426 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1427 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1428 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1429 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1430 : leunga 565 | leafEA _ = error "leafEA"
1431 :    
1432 : leunga 731 and int2real(ty, e) =
1433 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1434 :     in cleanupCode := !cleanupCode @ cleanup;
1435 :     (INTEGER, ty, ea)
1436 : george 545 end
1437 : leunga 731
1438 :     in gencode(su fexp);
1439 :     emits(!cleanupCode)
1440 : george 545 end (*reduceFexp*)
1441 : leunga 731
1442 :     (*========================================================
1443 :     * This section generates 3-address style floating
1444 :     * point code.
1445 :     *========================================================*)
1446 :    
1447 :     and isize 16 = I.I16
1448 :     | isize 32 = I.I32
1449 :     | isize _ = error "isize"
1450 :    
1451 :     and fstore''(fty, ea, d, mem, an) =
1452 :     (floatingPointUsed := true;
1453 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1454 :     src=foperand(fty, d)},
1455 :     an)
1456 :     )
1457 :    
1458 :     and fload''(fty, ea, mem, d, an) =
1459 :     (floatingPointUsed := true;
1460 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1461 :     dst=RealReg d}, an)
1462 :     )
1463 :    
1464 :     and fiload''(ity, ea, d, an) =
1465 :     (floatingPointUsed := true;
1466 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1467 :     )
1468 :    
1469 :     and fexpr''(e as T.FREG(_,f)) =
1470 :     if isFMemReg f then transFexpr e else f
1471 :     | fexpr'' e = transFexpr e
1472 :    
1473 :     and transFexpr e =
1474 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1475 :    
1476 :     (*
1477 :     * Process a floating point operand. Put operand in register
1478 :     * when possible. The operand should match the given fty.
1479 :     *)
1480 :     and foperand(fty, e as T.FREG(fty', f)) =
1481 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1482 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1483 :     foperand(fty, e) (* nop on the x86 *)
1484 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1485 :     (* fold operand when the precison matches *)
1486 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1487 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1488 :    
1489 :     (*
1490 :     * Process a floating point operand.
1491 :     * Try to fold in a memory operand or conversion from an integer.
1492 :     *)
1493 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1494 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1495 :     (REAL, fty, address(ea, mem), [])
1496 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1497 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1498 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1499 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1500 :    
1501 :     (* Generate binary operator. Since the real binary operators
1502 :     * does not take memory as destination, we also ensure this
1503 :     * does not happen.
1504 :     *)
1505 :     and fbinop(targetFty,
1506 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1507 :     (* Put the mem operand in rsrc *)
1508 :     let val _ = floatingPointUsed := true;
1509 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1510 :     | isMemOpnd(T.FLOAD _) = true
1511 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1512 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1513 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1514 :     | isMemOpnd _ = false
1515 :     val (binOp, ibinOp, lsrc, rsrc) =
1516 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1517 :     else (binOp, ibinOp, lsrc, rsrc)
1518 :     val lsrc = foperand(targetFty, lsrc)
1519 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1520 :     fun dstMustBeFreg f =
1521 :     if targetFty <> 64 then
1522 :     let val tmpR = newFreg()
1523 :     val tmp = I.FPR tmpR
1524 :     in mark(f tmp, an);
1525 :     emit(I.FMOVE{fsize=fsize targetFty,
1526 :     src=tmp, dst=RealReg fd})
1527 :     end
1528 :     else mark(f(RealReg fd), an)
1529 :     in case kind of
1530 :     REAL =>
1531 :     dstMustBeFreg(fn dst =>
1532 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1533 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1534 :     | INTEGER =>
1535 :     (dstMustBeFreg(fn dst =>
1536 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1537 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1538 :     emits code
1539 :     )
1540 :     end
1541 : george 545
1542 : leunga 731 and funop(fty, unOp, src, fd, an) =
1543 :     let val src = foperand(fty, src)
1544 :     in mark(I.FUNOP{fsize=fsize fty,
1545 :     unOp=unOp, src=src, dst=RealReg fd},an)
1546 :     end
1547 :    
1548 :     and doFexpr''(fty, e, fd, an) =
1549 :     case e of
1550 : george 889 T.FREG(_,fs) => if CB.sameColor(fs,fd) then ()
1551 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1552 :     (* Stupid x86 does everything as 80-bits internally. *)
1553 :    
1554 :     (* Binary operators *)
1555 :     | T.FADD(_, a, b) => fbinop(fty,
1556 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1557 :     a, b, fd, an)
1558 :     | T.FSUB(_, a, b) => fbinop(fty,
1559 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1560 :     a, b, fd, an)
1561 :     | T.FMUL(_, a, b) => fbinop(fty,
1562 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1563 :     a, b, fd, an)
1564 :     | T.FDIV(_, a, b) => fbinop(fty,
1565 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1566 :     a, b, fd, an)
1567 :    
1568 :     (* Unary operators *)
1569 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1570 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1571 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1572 :    
1573 :     (* Load *)
1574 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1575 :    
1576 :     (* Type conversions *)
1577 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1578 :     | T.CVTI2F(_, ty, e) =>
1579 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1580 :     in fiload''(ty, ea, fd, an);
1581 :     emits cleanup
1582 :     end
1583 :    
1584 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1585 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1586 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1587 :     | T.FEXT fexp =>
1588 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1589 :     | _ => error("doFexpr''")
1590 :    
1591 :     (*========================================================
1592 :     * Tie the two styles of fp code generation together
1593 :     *========================================================*)
1594 :     and fstore(fty, ea, d, mem, an) =
1595 :     if enableFastFPMode andalso !fast_floating_point
1596 :     then fstore''(fty, ea, d, mem, an)
1597 :     else fstore'(fty, ea, d, mem, an)
1598 :     and fload(fty, ea, d, mem, an) =
1599 :     if enableFastFPMode andalso !fast_floating_point
1600 :     then fload''(fty, ea, d, mem, an)
1601 :     else fload'(fty, ea, d, mem, an)
1602 :     and fexpr e =
1603 :     if enableFastFPMode andalso !fast_floating_point
1604 :     then fexpr'' e else fexpr' e
1605 :     and doFexpr(fty, e, fd, an) =
1606 :     if enableFastFPMode andalso !fast_floating_point
1607 :     then doFexpr''(fty, e, fd, an)
1608 :     else doFexpr'(fty, e, fd, an)
1609 :    
1610 : leunga 797 (*================================================================
1611 :     * Optimizations for x := x op y
1612 :     * Special optimizations:
1613 :     * Generate a binary operator, result must in memory.
1614 :     * The source must not be in memory
1615 :     *================================================================*)
1616 :     and binaryMem(binOp, src, dst, mem, an) =
1617 :     mark(I.BINARY{binOp=binOp, src=immedOrReg(operand src),
1618 :     dst=address(dst,mem)}, an)
1619 :     and unaryMem(unOp, opnd, mem, an) =
1620 :     mark(I.UNARY{unOp=unOp, opnd=address(opnd,mem)}, an)
1621 :    
1622 :     and isOne(T.LI n) = n = one
1623 :     | isOne _ = false
1624 :    
1625 :     (*
1626 :     * Perform optimizations based on recognizing
1627 :     * x := x op y or
1628 :     * x := y op x
1629 :     * first.
1630 :     *)
1631 :     and store(ty, ea, d, mem, an,
1632 :     {INC,DEC,ADD,SUB,NOT,NEG,SHL,SHR,SAR,OR,AND,XOR},
1633 :     doStore
1634 :     ) =
1635 :     let fun default() = doStore(ea, d, mem, an)
1636 :     fun binary1(t, t', unary, binary, ea', x) =
1637 :     if t = ty andalso t' = ty then
1638 :     if MLTreeUtils.eqRexp(ea, ea') then
1639 :     if isOne x then unaryMem(unary, ea, mem, an)
1640 :     else binaryMem(binary, x, ea, mem, an)
1641 :     else default()
1642 :     else default()
1643 :     fun unary(t,unOp, ea') =
1644 :     if t = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1645 :     unaryMem(unOp, ea, mem, an)
1646 :     else default()
1647 :     fun binary(t,t',binOp,ea',x) =
1648 :     if t = ty andalso t' = ty andalso
1649 :     MLTreeUtils.eqRexp(ea, ea') then
1650 :     binaryMem(binOp, x, ea, mem, an)
1651 :     else default()
1652 :    
1653 :     fun binaryCom1(t,unOp,binOp,x,y) =
1654 :     if t = ty then
1655 :     let fun again() =
1656 :     case y of
1657 :     T.LOAD(ty',ea',_) =>
1658 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1659 :     if isOne x then unaryMem(unOp, ea, mem, an)
1660 :     else binaryMem(binOp,x,ea,mem,an)
1661 :     else default()
1662 :     | _ => default()
1663 :     in case x of
1664 :     T.LOAD(ty',ea',_) =>
1665 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1666 :     if isOne y then unaryMem(unOp, ea, mem, an)
1667 :     else binaryMem(binOp,y,ea,mem,an)
1668 :     else again()
1669 :     | _ => again()
1670 :     end
1671 :     else default()
1672 :    
1673 :     fun binaryCom(t,binOp,x,y) =
1674 :     if t = ty then
1675 :     let fun again() =
1676 :     case y of
1677 :     T.LOAD(ty',ea',_) =>
1678 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1679 :     binaryMem(binOp,x,ea,mem,an)
1680 :     else default()
1681 :     | _ => default()
1682 :     in case x of
1683 :     T.LOAD(ty',ea',_) =>
1684 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1685 :     binaryMem(binOp,y,ea,mem,an)
1686 :     else again()
1687 :     | _ => again()
1688 :     end
1689 :     else default()
1690 :    
1691 :     in case d of
1692 :     T.ADD(t,x,y) => binaryCom1(t,INC,ADD,x,y)
1693 :     | T.SUB(t,T.LOAD(t',ea',_),x) => binary1(t,t',DEC,SUB,ea',x)
1694 :     | T.ORB(t,x,y) => binaryCom(t,OR,x,y)
1695 :     | T.ANDB(t,x,y) => binaryCom(t,AND,x,y)
1696 :     | T.XORB(t,x,y) => binaryCom(t,XOR,x,y)
1697 :     | T.SLL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHL,ea',x)
1698 :     | T.SRL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHR,ea',x)
1699 :     | T.SRA(t,T.LOAD(t',ea',_),x) => binary(t,t',SAR,ea',x)
1700 :     | T.NEG(t,T.LOAD(t',ea',_)) => unary(t,NEG,ea')
1701 :     | T.NOTB(t,T.LOAD(t',ea',_)) => unary(t,NOT,ea')
1702 :     | _ => default()
1703 :     end (* store *)
1704 :    
1705 : george 545 (* generate code for a statement *)
1706 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1707 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1708 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1709 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1710 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1711 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1712 : blume 839 | stmt(T.CALL{funct, targets, defs, uses, region, pops, ...}, an) =
1713 :     call(funct,targets,defs,uses,region,[],an, pops)
1714 :     | stmt(T.FLOW_TO(T.CALL{funct, targets, defs, uses, region, pops, ...},
1715 : leunga 796 cutTo), an) =
1716 : blume 839 call(funct,targets,defs,uses,region,cutTo,an, pops)
1717 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1718 : leunga 797 | stmt(T.STORE(8, ea, d, mem), an) =
1719 :     store(8, ea, d, mem, an, opcodes8, store8)
1720 :     | stmt(T.STORE(16, ea, d, mem), an) =
1721 :     store(16, ea, d, mem, an, opcodes16, store16)
1722 :     | stmt(T.STORE(32, ea, d, mem), an) =
1723 :     store(32, ea, d, mem, an, opcodes32, store32)
1724 :    
1725 : george 545 | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1726 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1727 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1728 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1729 : george 555 | stmt(T.EXT s, an) =
1730 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1731 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1732 :    
1733 :     and doStmt s = stmt(s, [])
1734 :     and doStmts ss = app doStmt ss
1735 :    
1736 :     and beginCluster' _ =
1737 :     ((* Must be cleared by the client.
1738 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1739 :     *)
1740 : leunga 731 floatingPointUsed := false;
1741 :     trapLabel := NONE;
1742 :     beginCluster 0
1743 :     )
1744 : george 545 and endCluster' a =
1745 : monnier 247 (case !trapLabel
1746 : monnier 411 of NONE => ()
1747 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1748 : monnier 411 (*esac*);
1749 : leunga 731 (* If floating point has been used allocate an extra
1750 :     * register just in case we didn't use any explicit register
1751 :     *)
1752 :     if !floatingPointUsed then (newFreg(); ())
1753 :     else ();
1754 : george 545 endCluster(a)
1755 :     )
1756 :    
1757 :     and reducer() =
1758 : george 984 TS.REDUCER{reduceRexp = expr,
1759 : george 545 reduceFexp = fexpr,
1760 :     reduceCCexp = ccExpr,
1761 :     reduceStm = stmt,
1762 :     operand = operand,
1763 :     reduceOperand = reduceOpnd,
1764 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1765 :     emit = mark,
1766 :     instrStream = instrStream,
1767 :     mltreeStream = self()
1768 :     }
1769 :    
1770 :     and self() =
1771 : george 984 TS.S.STREAM
1772 : leunga 815 { beginCluster = beginCluster',
1773 :     endCluster = endCluster',
1774 :     emit = doStmt,
1775 :     pseudoOp = pseudoOp,
1776 :     defineLabel = defineLabel,
1777 :     entryLabel = entryLabel,
1778 :     comment = comment,
1779 :     annotation = annotation,
1780 :     getAnnotations = getAnnotations,
1781 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1782 : george 545 }
1783 :    
1784 :     in self()
1785 : monnier 247 end
1786 :    
1787 : george 545 end (* functor *)
1788 :    
1789 :     end (* local *)

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0