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[smlnj] View of /sml/trunk/src/MLRISC/x86/ra/x86Rewrite.sml
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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 10380 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.
(* x86Rewrite.sml -- rewrite an alpha instruction 
 *
 * COPYRIGHT (c) 1997 Bell Labs
 *)
functor X86Rewrite(Instr : X86INSTR) : X86REWRITE = struct
  structure I=Instr
  structure C=I.C
  structure CB = CellsBasis
  fun error msg = MLRiscErrorMsg.error("X86Rewrite", msg)

  fun operand (rs,rt) opnd =
    (case opnd
     of I.Direct r => if CB.sameColor(r,rs) then I.Direct rt else opnd
      | I.Displace{base, disp, mem} => 
	  if CB.sameColor(base,rs) then I.Displace{base=rt, disp=disp, mem=mem} 
          else opnd
      | I.Indexed{base as SOME b, index, scale, disp, mem} => let
	  val base'= if CB.sameColor(b,rs) then SOME rt else base
	  val index'=if CB.sameColor(index,rs) then rt else index
	in I.Indexed{base=base', index=index', scale=scale, disp=disp, mem=mem}
	end
      | I.Indexed{base, index, scale, disp, mem=mem}  => 
	if CB.sameColor(index,rs) then 
	  I.Indexed{base=base, index=rt, scale=scale, disp=disp, mem=mem}
	else opnd
      | _ => opnd
    (*esac*))

  fun rewriteUse(instr, rs, rt) = let
    val operand = operand (rs, rt)
    fun replace r = if CB.sameColor(r,rs) then rt else r
    fun rewriteX86Use(instr) = 
     (case instr
      of I.JMP(opnd, labs) => I.JMP(operand opnd, labs)
       | I.JCC{cond, opnd} => I.JCC{cond=cond, opnd = operand opnd}
       | I.CALL{opnd, defs, uses, return, cutsTo, mem, pops} => 
	   I.CALL{opnd=operand opnd, defs=defs, return=return,
		  uses=CB.CellSet.map {from=rs,to=rt} uses, cutsTo=cutsTo,
		  mem=mem, pops=pops}
       | I.MOVE{mvOp, src, dst as I.Direct _} => 
	   I.MOVE{mvOp=mvOp, src=operand src, dst=dst}
       | I.MOVE{mvOp, src, dst} => 
	   I.MOVE{mvOp=mvOp, src=operand src, dst=operand dst}
       | I.LEA{r32, addr} => I.LEA{r32=r32, addr=operand addr}
       | I.CMPL{lsrc, rsrc} => I.CMPL{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.CMPW{lsrc, rsrc} => I.CMPW{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.CMPB{lsrc, rsrc} => I.CMPB{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.TESTL{lsrc, rsrc} => I.TESTL{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.TESTW{lsrc, rsrc} => I.TESTW{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.TESTB{lsrc, rsrc} => I.TESTB{lsrc=operand lsrc, rsrc=operand rsrc}
       | I.BITOP{bitOp, lsrc, rsrc} => 
	  I.BITOP{bitOp=bitOp, lsrc=operand lsrc, rsrc=operand rsrc}
       | I.BINARY{binOp, src, dst} => 
	  I.BINARY{binOp=binOp, src=operand src, dst=operand dst}
       | I.CMPXCHG{lock, sz, src, dst} => 
	  I.CMPXCHG{lock=lock, sz=sz, src=operand src, dst=operand dst}
       | I.MULTDIV{multDivOp, src} => 
	  I.MULTDIV{multDivOp=multDivOp, src=operand src}
       | I.MUL3{dst, src1, src2} => 
	  I.MUL3{dst=dst, src1=operand src1, src2=src2}
       | I.UNARY{unOp, opnd} => I.UNARY{unOp=unOp, opnd=operand opnd}
       | I.SET{cond, opnd} => I.SET{cond=cond, opnd=operand opnd}
       | I.PUSHL opnd => I.PUSHL(operand opnd)
       | I.PUSHW opnd => I.PUSHW(operand opnd)
       | I.PUSHB opnd => I.PUSHB(operand opnd)
       | I.POP opnd  => I.POP(operand opnd)
       | I.COPY{dst, src, tmp} => 
	  I.COPY{dst=dst, src=map replace src, tmp=tmp}
       | I.FSTPT opnd => I.FSTPT(operand opnd)
       | I.FSTPL opnd => I.FSTPL(operand opnd)
       | I.FSTPS opnd => I.FSTPS(operand opnd)
       | I.FSTL opnd => I.FSTL(operand opnd)
       | I.FSTS opnd => I.FSTS(operand opnd)
       | I.FLDT opnd => I.FLDT(operand opnd)
       | I.FLDL opnd => I.FLDL(operand opnd)
       | I.FLDS opnd => I.FLDS(operand opnd)
       | I.FUCOM opnd => I.FUCOM(operand opnd)
       | I.FUCOMP opnd => I.FUCOMP(operand opnd)
       | I.FENV{fenvOp,opnd} => I.FENV{fenvOp=fenvOp, opnd=operand opnd}
       | I.FBINARY{binOp, src, dst} => 
	  I.FBINARY{binOp=binOp, src=operand src, dst=dst}
       | I.FIBINARY{binOp, src} => 
	  I.FIBINARY{binOp=binOp, src=operand src}

	 (* Pseudo floating point instructions *)
       | I.FMOVE{fsize,src,dst} => 
	  I.FMOVE{fsize=fsize,src=operand src,dst=operand dst}
       | I.FILOAD{isize,ea,dst} => 
	  I.FILOAD{isize=isize,ea=operand ea,dst=operand dst}
       | I.FBINOP{fsize,binOp,lsrc,rsrc,dst} =>
	  I.FBINOP{fsize=fsize,binOp=binOp,
		   lsrc=operand lsrc,rsrc=operand rsrc,dst=operand dst}
       | I.FIBINOP{isize,binOp,lsrc,rsrc,dst} =>
	  I.FIBINOP{isize=isize,binOp=binOp,
		    lsrc=operand lsrc,rsrc=operand rsrc,dst=operand dst}
       | I.FUNOP{fsize,unOp,src,dst} =>
	  I.FUNOP{fsize=fsize,unOp=unOp,src=operand src,dst=operand dst}
       | I.FCMP{fsize,lsrc,rsrc} =>
	  I.FCMP{fsize=fsize,lsrc=operand lsrc,rsrc=operand rsrc}

       | I.CMOV{cond, src, dst} => I.CMOV{cond=cond, src=operand src, dst=dst}
       | _ => instr
    (*esac*))

    fun f(I.ANNOTATION{a,i}) = 
	 I.ANNOTATION{i=rewriteUse(i, rs, rt),
		      a = case a of
			     CB.DEF_USE{cellkind=CB.GP,defs,uses} =>
			       CB.DEF_USE{cellkind=CB.GP,uses=map replace uses,
					 defs=defs}
			    | _ => a}
      | f(I.INSTR i) = I.INSTR(rewriteX86Use(i))
      | f _  = error "rewriteUse:f"
  in f (instr:I.instruction)
  end

  fun rewriteDef(instr, rs, rt) = let
    fun operand(opnd as I.Direct r) = 
	if CB.sameColor(r,rs) then I.Direct rt else opnd
    fun replace r = if CB.sameColor(r,rs) then rt else r
    fun rewriteX86Def(instr) =
     (case instr 
      of I.CALL{opnd, defs, uses, return, cutsTo, mem, pops} => 
	   I.CALL{opnd=opnd, cutsTo=cutsTo, 
		  return=CB.CellSet.map {from=rs,to=rt} return, pops=pops,
		  defs=CB.CellSet.map {from=rs,to=rt} defs, uses=uses, mem=mem}
       | I.MOVE{mvOp, src, dst} => I.MOVE{mvOp=mvOp, src=src, dst=operand dst}
       | I.LEA{r32, addr} => I.LEA{r32=replace r32, addr=addr}
       | I.BINARY{binOp, src, dst} => I.BINARY{binOp=binOp, src=src, dst=operand dst}
       | I.CMPXCHG{lock, sz, src, dst} => 
	  I.CMPXCHG{lock=lock, sz=sz, src=src, dst=operand dst}
       | I.MUL3{dst, src1, src2} => I.MUL3{dst=replace dst, src1=src1, src2=src2}
       | I.UNARY{unOp, opnd} => I.UNARY{unOp=unOp, opnd=operand opnd}
       | I.SET{cond, opnd} => I.SET{cond=cond, opnd=operand opnd}
       | I.COPY{dst, src, tmp} => I.COPY{dst=map replace dst, src=src, tmp=tmp}
       | I.CMOV{cond, src, dst} => I.CMOV{cond=cond, src=src, dst=replace dst}
       | _ => instr
    (*esac*))

    fun f (I.ANNOTATION{a,i}) =
	   I.ANNOTATION{i=rewriteDef(i,rs,rt),
			  a=(case a of
			      CB.DEF_USE{cellkind=CB.GP,defs,uses} =>
			        CB.DEF_USE{cellkind=CB.GP,uses=uses,
				 	   defs=map replace defs}
			     | _ => a)}
      | f (I.INSTR i) = I.INSTR(rewriteX86Def(i))
      | f _ = error "rewriteDef:f"
  in f(instr)
  end

  fun frewriteUse(instr, fs, ft) = let
    fun foperand(opnd as I.FDirect f) = 
	   if CB.sameColor(f,fs) then I.FDirect ft else opnd
      | foperand(opnd as I.FPR f) = 
	   if CB.sameColor(f,fs) then I.FPR ft else opnd
      | foperand opnd = opnd

    fun replace f = if CB.sameColor(f,fs) then ft else f
    fun frewriteX86Use(instr) = 
     (case instr
      of I.FCOPY{dst, src, tmp,...} => I.FCOPY{dst=dst, src=map replace src, tmp=tmp}
       | I.FLDL opnd => I.FLDL(foperand opnd)
       | I.FLDS opnd => I.FLDS(foperand opnd)
       | I.CALL{opnd, defs, uses, return, cutsTo, mem, pops} => 
	   I.CALL{opnd=opnd, defs=defs, return=return, cutsTo=cutsTo,
		  uses=CB.CellSet.map {from=fs, to=ft} uses, mem=mem, pops=pops }
       | I.FBINARY{binOp, src, dst} => 
	   I.FBINARY{binOp=binOp, src=foperand src, dst=foperand dst}
       | I.FUCOM opnd => I.FUCOM(foperand opnd)
       | I.FUCOMP opnd => I.FUCOMP(foperand opnd)

	 (* Pseudo floating point instructions *)
       | I.FMOVE{fsize,dst,src} =>
	  I.FMOVE{fsize=fsize,dst=dst,src=foperand src}
       | I.FBINOP{fsize,binOp,lsrc,rsrc,dst} =>
	  I.FBINOP{fsize=fsize,binOp=binOp,
		   lsrc=foperand lsrc,rsrc=foperand rsrc,dst=dst}
       | I.FIBINOP{isize,binOp,lsrc,rsrc,dst} =>
	  I.FIBINOP{isize=isize,binOp=binOp,
		    lsrc=foperand lsrc,rsrc=foperand rsrc,dst=dst}
       | I.FUNOP{fsize,unOp,src,dst} =>
	  I.FUNOP{fsize=fsize,unOp=unOp,src=foperand src,dst=dst}
       | I.FCMP{fsize,lsrc,rsrc} =>
	  I.FCMP{fsize=fsize,lsrc=foperand lsrc,rsrc=foperand rsrc}
       | _ => instr
    (*esac*))

    fun f(I.ANNOTATION{a, i}) = 
	   I.ANNOTATION{i=frewriteUse(i,fs,ft),
			  a=case a of
			     CB.DEF_USE{cellkind=CB.FP,defs,uses} =>
			       CB.DEF_USE{cellkind=CB.FP,uses=map replace uses,
					 defs=defs}
			    | _ => a}
      | f(I.INSTR i) = I.INSTR(frewriteX86Use(i))
      | f _ = error "frewrite"
  in f(instr)
  end

  fun frewriteDef(instr, fs, ft) = let
    fun foperand(opnd as I.FDirect r) = 
	 if CB.sameColor(r,fs) then I.FDirect ft else opnd
      | foperand(opnd as I.FPR r) = 
	 if CB.sameColor(r,fs) then I.FPR ft else opnd
      | foperand opnd = opnd
    fun replace f = if CB.sameColor(f,fs) then ft else f
    fun frewriteX86Def(instr) = 
     (case instr
      of I.FCOPY{dst, src, tmp, ...} => I.FCOPY{dst=map replace dst, src=src, tmp=tmp}
       | I.FSTPT opnd => I.FSTPT(foperand opnd)
       | I.FSTPL opnd => I.FSTPL(foperand opnd)
       | I.FSTPS opnd => I.FSTPS(foperand opnd)
       | I.FSTL opnd => I.FSTL(foperand opnd)
       | I.FSTS opnd => I.FSTS(foperand opnd)
       | I.CALL{opnd, defs, uses, return, cutsTo, mem, pops} => 
	   I.CALL{opnd=opnd, defs=CB.CellSet.map {from=fs, to=ft} defs, 
			     return=CB.CellSet.map {from=fs, to=ft} return,
		  uses=uses, cutsTo=cutsTo, mem=mem, pops=pops}
       | I.FBINARY{binOp, src, dst} => I.FBINARY{binOp=binOp, src=src, dst=foperand dst}

	 (* Pseudo floating point instructions *)
       | I.FMOVE{fsize,src,dst} => 
	  I.FMOVE{fsize=fsize,src=src,dst=foperand dst}
       | I.FILOAD{isize,ea,dst} => 
	  I.FILOAD{isize=isize,ea=ea,dst=foperand dst}
       | I.FBINOP{fsize,binOp,lsrc,rsrc,dst} =>
	  I.FBINOP{fsize=fsize,binOp=binOp,lsrc=lsrc,rsrc=rsrc,dst=foperand dst}
       | I.FIBINOP{isize,binOp,lsrc,rsrc,dst} =>
	  I.FIBINOP{isize=isize,binOp=binOp,lsrc=lsrc,rsrc=rsrc,dst=foperand dst}
       | I.FUNOP{fsize,unOp,src,dst} =>
	  I.FUNOP{fsize=fsize,unOp=unOp,src=src,dst=foperand dst}
       | _  => instr
    (*esac*))

    fun f(I.ANNOTATION{i,a}) =
	   I.ANNOTATION{i=frewriteDef(i,fs,ft),
			  a=case a of
			     CB.DEF_USE{cellkind=CB.FP,defs,uses} =>
			       CB.DEF_USE{cellkind=CB.FP,uses=uses,
					 defs=map replace defs}
			    | _ => a}
      | f(I.INSTR(i)) = I.INSTR(frewriteX86Def(i))
      | f _ = error "frewriteDef"
  in f(instr)
  end
end


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