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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/x86.md
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Annotation of /sml/trunk/src/MLRISC/x86/x86.md

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1 : monnier 409 (*
2 :     * 32bit, x86 instruction set.
3 :     *)
4 :     architecture X86 =
5 :     struct
6 :    
7 :     name "X86"
8 :    
9 :     superscalar
10 :    
11 :     little endian (* is this right??? *)
12 :    
13 :     lowercase assembly
14 :    
15 :     (*
16 :     * Assembly note:
17 :     * Note: we are using the AT&T syntax (for Linux) and not the intel syntax
18 :     * memory operands have the form:
19 :     * section:disp(base, index, scale)
20 :     * Most of the complication is actually in emiting the correct
21 :     * operand syntax.
22 :     *)
23 :    
24 :     (* Note: While the x86 has only 8 integer and 8 floating point registers,
25 :     * the SMLNJ compiler fakes it by assuming that it has 32 integer
26 :     * and 32 floating point registers. That's why we
27 :     *)
28 :    
29 :     storage
30 : george 545 GP "r" = 32 cells of 32 bits in cellset called "register"
31 :     assembly as
32 :     (fn (0,8) => "%al"
33 :     | (0,16) => "%ax"
34 :     | (0,32) => "%eax"
35 :     | (1,8) => "%cl"
36 :     | (1,16) => "%cx"
37 :     | (1,32) => "%ecx"
38 :     | (2,8) => "%dl"
39 :     | (2,16) => "%dx"
40 :     | (2,32) => "%edx"
41 :     | (3,8) => "%bl"
42 :     | (3,16) => "%bx"
43 :     | (3,32) => "%ebx"
44 :     | (4,16) => "%sp"
45 :     | (4,32) => "%esp"
46 :     | (5,16) => "%bp"
47 :     | (5,32) => "%ebp"
48 :     | (6,16) => "%si"
49 :     | (6,32) => "%esi"
50 :     | (7,16) => "%di"
51 :     | (7,32) => "%edi"
52 :     | (r,_) => "%"^Int.toString r
53 : monnier 409 )
54 : george 545 | FP "f" = 32 cells of 80 bits in cellset called "floating point register"
55 :     assembly as (fn (f,_) =>
56 :     if f = 0 then "%st"
57 :     else if f < 8 then "%st("^Int.toString f^")"
58 :     else "%f"^Int.toString f
59 :     (* pseudo register *)
60 :     )
61 :     | CC "cc" = cells of 32 bits in cellset called "condition code register"
62 :     assembly as "cc"
63 :     | MEM "m" = cells of 8 bits called "memory"
64 :     assembly as (fn (r,_) => "m"^Int.toString r)
65 :     | CTRL "ctrl" = cells of 8 bits called "control"
66 :     assembly as (fn (r,_) => "ctrl"^Int.toString r)
67 :    
68 : monnier 409 locations
69 :     eax = $GP[0]
70 :     and ecx = $GP[1]
71 :     and edx = $GP[2]
72 :     and ebx = $GP[3]
73 :     and esp = $GP[4]
74 :     and ebp = $GP[5]
75 :     and esi = $GP[6]
76 :     and edi = $GP[7]
77 : monnier 429 and stackptrR = $GP[4]
78 : george 545 and ST(x) = $FP[x]
79 : monnier 409 and asmTmpR = ~1 (* not used *)
80 :     and fasmTmp = ~1 (* not used *)
81 :    
82 : george 545 structure RTL =
83 : monnier 409 struct
84 : george 545 end
85 : monnier 409
86 :     structure Instruction = struct
87 :     (* An effective address can be any combination of
88 :     * base + index*scale + disp
89 :     * or
90 :     * B + I*SCALE + DISP
91 :     *
92 :     * where any component is optional. The operand datatype captures
93 :     * all these combinations.
94 :     *
95 :     * DISP == Immed | ImmedLabel | Const
96 :     * B == Displace{base=B, disp=0}
97 :     * B+DISP == Displace{base=B, disp=DISP}
98 :     * I*SCALE+DISP == Indexed{base=NONE, index=I, scale=SCALE, disp=D}
99 :     * B+I*SCALE+DISP == Indexed{base=SOME B, index=I, scale=SCALE, disp=DISP}
100 :     *
101 :     * Note1: The index register cannot be EBP.
102 :     * The disp field must be one of Immed, ImmedLabel, or Const.
103 :     *)
104 :    
105 :     (* Note: Relative is only generated after sdi resolution *)
106 :     datatype operand =
107 :     Immed of Int32.int
108 :     | ImmedLabel of LabelExp.labexp
109 :     | Relative of int
110 :     | LabelEA of LabelExp.labexp
111 :     | Direct of $GP
112 :     | FDirect of $FP
113 : monnier 498 | MemReg of int (* pseudo memory register *)
114 : monnier 409 | Displace of {base: $GP, disp:operand, mem:Region.region}
115 :     | Indexed of {base: $GP option, index: $GP, scale:int, disp:operand,
116 :     mem:Region.region}
117 : george 545
118 :     type addressing_mode = operand
119 : monnier 409
120 :     type ea = operand
121 :    
122 : george 545 datatype cond! =
123 :     EQ "e" | NE | LT "l" | LE | GT "g" | GE
124 :     | B | BE (* below *) | A | AE (* above *)
125 :     | C | NC (* if carry *)| P | NP (* if parity *)
126 :     | O | NO (* overflow *)
127 : monnier 409
128 : george 545 datatype binaryOp! =
129 :     ADDL | SUBL | ANDL | ORL | XORL | SHLL | SARL | SHRL | ADCL | SBBL
130 :     | ADDW | SUBW | ANDW | ORW | XORW | SHLW | SARW | SHRW
131 :     | ADDB | SUBB | ANDB | ORB | XORB | SHLB | SARB | SHRB
132 :    
133 : monnier 409 datatype multDivOp! = UMUL | IDIV | UDIV
134 :    
135 : george 545 datatype unaryOp! = DECL | INCL | NEGL | NOTL | NOTW | NOTB
136 : monnier 409
137 : george 545 datatype move! = MOVL
138 :     | MOVB
139 :     | MOVW
140 :     | MOVSWL | MOVZWL (* word -> long *)
141 :     | MOVSBL | MOVZBL (* byte -> long *)
142 : monnier 409
143 :     (* The Intel manual is incorrect on the description of FDIV and FDIVR *)
144 :     datatype fbinOp! =
145 : george 545 FADDP | FADD | FIADD
146 :     | FMULP | FMUL | FIMUL
147 :     | FSUBP | FSUB | FISUB (* ST(1) := ST-ST(1); [pop] *)
148 :     | FSUBRP | FSUBR | FISUBR (* ST(1) := ST(1)-ST; [pop] *)
149 :     | FDIVP | FDIV | FIDIV (* ST(1) := ST/ST(1); [pop] *)
150 :     | FDIVRP | FDIVR | FIDIVR (* ST(1) := ST(1)/ST; [pop] *)
151 : monnier 409
152 :     datatype funOp! = FABS | FCHS
153 : george 545 | FSIN | FCOS | FTAN
154 :     | FSCALE | FRNDINT | FSQRT
155 :     | FTST | FXAM
156 :     | FINCSTP | FDECSTP
157 : monnier 409
158 : george 545 datatype fenvOp! = FLDENV | FNLDENV | FSTENV | FNSTENV
159 :    
160 : monnier 409 end (* struct Instruction *)
161 :    
162 :     (* A bunch of routines for emitting assembly *)
163 :     functor Assembly
164 :     (structure MemRegs : MEMORY_REGISTERS where I = Instr) =
165 :     struct
166 :     val memReg = MemRegs.memReg regmap
167 : monnier 429 fun emitInt32 i =
168 :     let val s = Int32.toString i
169 :     val s = if i >= 0 then s else "-"^String.substring(s,1,size s-1)
170 :     in emit s end
171 :    
172 : monnier 409 fun emitScale 0 = emit "1"
173 :     | emitScale 1 = emit "2"
174 :     | emitScale 2 = emit "4"
175 :     | emitScale 3 = emit "8"
176 :     | emitScale _ = error "emitScale"
177 :    
178 :     and eImmed(I.Immed (i)) = emitInt32 i
179 :     | eImmed(I.ImmedLabel lexp) = emit_labexp lexp
180 :     | eImmed _ = error "eImmed"
181 :    
182 :     and emit_operand opn =
183 :     case opn of
184 :     I.Immed i => (emit "$"; emitInt32 i)
185 :     | I.ImmedLabel lexp => (emit "$"; emit_labexp lexp)
186 :     | I.LabelEA le => emit_labexp le
187 :     | I.Relative _ => error "emit_operand"
188 :     | I.Direct r => emit_GP r
189 : monnier 498 | I.MemReg r => emit_operand(memReg opn)
190 : monnier 409 | I.FDirect f =>
191 :     let val f' = regmap f
192 :     in if f' < (32+8) then emit_FP f' else emit_operand(memReg opn) end
193 :     | I.Displace{base,disp,mem,...} =>
194 : george 545 (emit_disp disp; emit "("; emit_GP base; emit ")";
195 : monnier 409 emit_region mem)
196 :     | I.Indexed{base=NONE,index,scale,disp,mem,...} =>
197 : george 545 (emit_disp disp; emit "("; emit_GP index; comma();
198 :     emitScale scale; emit ")"; emit_region mem)
199 : monnier 409 | I.Indexed{base=SOME base,index,scale,disp,mem,...} =>
200 : george 545 (emit_disp disp; emit "("; emit_GP base;
201 : monnier 429 comma(); emit_GP index; comma(); emitScale scale; emit ")";
202 : monnier 409 emit_region mem)
203 :    
204 : george 545 and emit_disp(I.Immed 0) = ()
205 :     | emit_disp(I.Immed i) = emitInt32 i
206 :     | emit_disp(I.ImmedLabel lexp) = emit_labexp lexp
207 :     | emit_disp _ = error "emit_disp"
208 :    
209 : monnier 409 (* The gas assembler does not like the "$" prefix for immediate
210 :     * labels in certain instructions.
211 :     *)
212 :     fun stupidGas(I.ImmedLabel lexp) = emit_labexp lexp
213 :     | stupidGas(I.LabelEA _) = error "stupidGas"
214 :     | stupidGas opnd = emit_operand opnd
215 :    
216 :     val emit_dst = emit_operand
217 :     val emit_src = emit_operand
218 :     val emit_opnd = emit_operand
219 :     val emit_rsrc = emit_operand
220 :     val emit_lsrc = emit_operand
221 :     val emit_addr = emit_operand
222 : george 545 val emit_src1 = emit_operand
223 :     end (* Instruction *)
224 : monnier 409
225 :     (* many of these instructions imply certain register usages *)
226 :     instruction
227 :     NOP
228 :     ``nop''
229 :    
230 :     | JMP of operand * Label.label list
231 :     ``jmp\t<stupidGas operand>''
232 :    
233 :     | JCC of {cond:cond, opnd:operand}
234 : george 545 ``j<cond>\t<stupidGas opnd>''
235 : monnier 409
236 :     | CALL of operand * C.cellset * C.cellset * Region.region
237 : monnier 498 ``call\t<stupidGas operand><region><
238 :     emit_defs(cellset1)><
239 :     emit_uses(cellset2)>''
240 : monnier 409
241 : george 545 | LEAVE
242 :     ``leave''
243 :    
244 : monnier 429 | RET of operand option
245 :     ``ret<case operand of NONE => ()
246 :     | SOME e => (emit "\t"; emit_operand e)>''
247 : monnier 409
248 :     (* integer *)
249 :     | MOVE of {mvOp:move, src:operand, dst:operand}
250 :     ``<mvOp>\t<src>, <dst>''
251 :    
252 :     | LEA of {r32: $GP, addr: operand}
253 :     ``leal\t<addr>, <r32>''
254 :    
255 : george 545 | CMPL of {lsrc: operand, rsrc: operand}
256 : monnier 409 ``cmpl\t<rsrc>, <lsrc>''
257 :    
258 : george 545 | CMPW of {lsrc: operand, rsrc: operand}
259 :     ``cmpb\t<rsrc>, <lsrc>''
260 :    
261 :     | CMPB of {lsrc: operand, rsrc: operand}
262 :     ``cmpb\t<rsrc>, <lsrc>''
263 :    
264 :     | TESTL of {lsrc: operand, rsrc: operand}
265 :     ``testl\t<rsrc>, <lsrc>''
266 :    
267 :     | TESTW of {lsrc: operand, rsrc: operand}
268 :     ``testw\t<rsrc>, <lsrc>''
269 :    
270 :     | TESTB of {lsrc: operand, rsrc: operand}
271 :     ``testb\t<rsrc>, <lsrc>''
272 :    
273 : monnier 409 | BINARY of {binOp:binaryOp, src:operand, dst:operand}
274 : george 545 asm: (case (src,binOp) of
275 :     (I.Direct _,
276 :     (I.SARL | I.SHRL | I.SHLL |
277 :     I.SARW | I.SHRW | I.SHLW |
278 :     I.SARB | I.SHRB | I.SHLB)) => ``<binOp>\t%cl, <dst>''
279 :     | _ => ``<binOp>\t<src>, <dst>''
280 :     )
281 : monnier 409
282 :     | MULTDIV of {multDivOp:multDivOp, src:operand}
283 :     ``<multDivOp>l\t<src>''
284 :    
285 : george 545 | MUL3 of {dst: $GP, src2: Int32.int option, src1:operand}
286 :     (* Fermin: constant operand must go first *)
287 :     asm: (case src2 of
288 :     NONE => ``imul\t<src1>, <dst>''
289 :     | SOME i => ``imul\t$<emitInt32 i>, <src1>, <dst>''
290 :     )
291 : monnier 409
292 :     | UNARY of {unOp:unaryOp, opnd:operand}
293 : george 545 ``<unOp>\t<opnd>''
294 : monnier 409
295 : george 545 (* set byte on condition code; note that
296 :     * this only sets the low order byte, so it also
297 :     * uses its operand.
298 :     *)
299 :     | SET of {cond:cond, opnd:operand}
300 :     ``set<cond>\t<opnd>''
301 :    
302 :     (* conditional move; Pentium Pro or higher only
303 :     * Destination must be a register.
304 :     *)
305 :     | CMOV of {cond:cond, src:operand, dst: $GP}
306 :     ``cmov<cond>\t<src>, <dst>''
307 :    
308 :     | PUSHL of operand
309 : monnier 409 ``pushl\t<operand>''
310 :    
311 : george 545 | PUSHW of operand
312 :     ``pushw\t<operand>''
313 :    
314 :     | PUSHB of operand
315 :     ``pushb\t<operand>''
316 :    
317 : monnier 409 | POP of operand
318 :     ``popl\t<operand>''
319 :    
320 :     | CDQ
321 :     ``cdq''
322 :    
323 :     | INTO
324 :     ``into''
325 :    
326 :     (* parallel copies *)
327 :     | COPY of {dst: $GP list, src: $GP list, tmp:operand option}
328 : george 545 asm: emitInstrs (Shuffle.shuffle{regmap,tmp,dst,src})
329 :    
330 : monnier 409 | FCOPY of {dst: $FP list, src: $FP list, tmp:operand option}
331 : george 545 asm: emitInstrs (Shuffle.shufflefp{regmap,tmp,dst,src})
332 : monnier 409
333 :     (* floating *)
334 :     | FBINARY of {binOp:fbinOp, src:operand, dst:operand}
335 :     ``<binOp>\t<src>, <dst>''
336 :    
337 :     | FUNARY of funOp
338 :     ``<funOp>''
339 :    
340 :     | FUCOMPP
341 :     ``fucompp''
342 :    
343 : george 545 | FCOM
344 :     ``fcom''
345 : monnier 409
346 : george 545 | FCOMPP
347 :     ``fcompp''
348 : monnier 409
349 : george 545 | FXCH of {opnd: $FP}
350 :     asm: (``fxch\t''; if opnd = C.ST(1) then () else ``<opnd>'')
351 : monnier 409
352 : george 545 | FSTPL of operand
353 :     ``fstpl\t<operand>''
354 :    
355 :     | FSTPS of operand
356 :     ``fstps\t<operand>''
357 :    
358 :     | FLDL of operand
359 :     ``fldl\t<operand>''
360 :    
361 :     | FLDS of operand
362 :     ``flds\t<operand>''
363 :    
364 : monnier 409 | FILD of operand
365 :     ``fild\t<operand>''
366 :    
367 :     | FNSTSW
368 :     ``fnstsw''
369 :    
370 : george 545 | FENV of {fenvOp:fenvOp, opnd:operand} (* load/store environment *)
371 :     ``<fenvOp>\t<opnd>''
372 :    
373 : monnier 409 (* misc *)
374 :     | SAHF
375 :     ``sahf''
376 :    
377 :     (* annotations *)
378 :     | ANNOTATION of {i:instruction, a:Annotations.annotation}
379 : george 545 asm: (emitInstr i; comment(Annotations.toString a))
380 : monnier 409 end
381 :    

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