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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/x86.md
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Annotation of /sml/trunk/src/MLRISC/x86/x86.md

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1 : monnier 409 (*
2 :     * 32bit, x86 instruction set.
3 :     *)
4 :     architecture X86 =
5 :     struct
6 :    
7 :     name "X86"
8 :    
9 :     superscalar
10 :    
11 :     little endian (* is this right??? *)
12 :    
13 :     lowercase assembly
14 :    
15 :     (*
16 :     * Assembly note:
17 :     * Note: we are using the AT&T syntax (for Linux) and not the intel syntax
18 :     * memory operands have the form:
19 :     * section:disp(base, index, scale)
20 :     * Most of the complication is actually in emiting the correct
21 :     * operand syntax.
22 :     *)
23 :    
24 :     (* Note: While the x86 has only 8 integer and 8 floating point registers,
25 :     * the SMLNJ compiler fakes it by assuming that it has 32 integer
26 :     * and 32 floating point registers. That's why we
27 :     *)
28 :    
29 :     storage
30 : george 545 GP "r" = 32 cells of 32 bits in cellset called "register"
31 :     assembly as
32 :     (fn (0,8) => "%al"
33 :     | (0,16) => "%ax"
34 :     | (0,32) => "%eax"
35 :     | (1,8) => "%cl"
36 :     | (1,16) => "%cx"
37 :     | (1,32) => "%ecx"
38 :     | (2,8) => "%dl"
39 :     | (2,16) => "%dx"
40 :     | (2,32) => "%edx"
41 :     | (3,8) => "%bl"
42 :     | (3,16) => "%bx"
43 :     | (3,32) => "%ebx"
44 :     | (4,16) => "%sp"
45 :     | (4,32) => "%esp"
46 :     | (5,16) => "%bp"
47 :     | (5,32) => "%ebp"
48 :     | (6,16) => "%si"
49 :     | (6,32) => "%esi"
50 :     | (7,16) => "%di"
51 :     | (7,32) => "%edi"
52 :     | (r,_) => "%"^Int.toString r
53 : monnier 409 )
54 : george 545 | FP "f" = 32 cells of 80 bits in cellset called "floating point register"
55 : leunga 565 assembly as (fn (0,_) => "%st"
56 :     | (f,_) =>
57 :     if f < 8 then "%st("^Int.toString f^")"
58 :     else "%f"^Int.toString f
59 :     (* pseudo register *)
60 : george 545 )
61 :     | CC "cc" = cells of 32 bits in cellset called "condition code register"
62 :     assembly as "cc"
63 :     | MEM "m" = cells of 8 bits called "memory"
64 :     assembly as (fn (r,_) => "m"^Int.toString r)
65 :     | CTRL "ctrl" = cells of 8 bits called "control"
66 :     assembly as (fn (r,_) => "ctrl"^Int.toString r)
67 :    
68 : monnier 409 locations
69 :     eax = $GP[0]
70 :     and ecx = $GP[1]
71 :     and edx = $GP[2]
72 :     and ebx = $GP[3]
73 :     and esp = $GP[4]
74 :     and ebp = $GP[5]
75 :     and esi = $GP[6]
76 :     and edi = $GP[7]
77 : monnier 429 and stackptrR = $GP[4]
78 : george 545 and ST(x) = $FP[x]
79 : monnier 409 and asmTmpR = ~1 (* not used *)
80 :     and fasmTmp = ~1 (* not used *)
81 :    
82 : george 545 structure RTL =
83 : monnier 409 struct
84 : george 545 end
85 : monnier 409
86 :     structure Instruction = struct
87 :     (* An effective address can be any combination of
88 :     * base + index*scale + disp
89 :     * or
90 :     * B + I*SCALE + DISP
91 :     *
92 :     * where any component is optional. The operand datatype captures
93 :     * all these combinations.
94 :     *
95 :     * DISP == Immed | ImmedLabel | Const
96 :     * B == Displace{base=B, disp=0}
97 :     * B+DISP == Displace{base=B, disp=DISP}
98 :     * I*SCALE+DISP == Indexed{base=NONE, index=I, scale=SCALE, disp=D}
99 :     * B+I*SCALE+DISP == Indexed{base=SOME B, index=I, scale=SCALE, disp=DISP}
100 :     *
101 :     * Note1: The index register cannot be EBP.
102 :     * The disp field must be one of Immed, ImmedLabel, or Const.
103 :     *)
104 :    
105 :     (* Note: Relative is only generated after sdi resolution *)
106 :     datatype operand =
107 :     Immed of Int32.int
108 :     | ImmedLabel of LabelExp.labexp
109 :     | Relative of int
110 :     | LabelEA of LabelExp.labexp
111 :     | Direct of $GP
112 :     | FDirect of $FP
113 : george 555 | ST of $FP
114 : monnier 498 | MemReg of int (* pseudo memory register *)
115 : monnier 409 | Displace of {base: $GP, disp:operand, mem:Region.region}
116 :     | Indexed of {base: $GP option, index: $GP, scale:int, disp:operand,
117 :     mem:Region.region}
118 : george 545
119 :     type addressing_mode = operand
120 : monnier 409
121 :     type ea = operand
122 :    
123 : george 545 datatype cond! =
124 :     EQ "e" | NE | LT "l" | LE | GT "g" | GE
125 :     | B | BE (* below *) | A | AE (* above *)
126 :     | C | NC (* if carry *)| P | NP (* if parity *)
127 :     | O | NO (* overflow *)
128 : monnier 409
129 : george 545 datatype binaryOp! =
130 :     ADDL | SUBL | ANDL | ORL | XORL | SHLL | SARL | SHRL | ADCL | SBBL
131 :     | ADDW | SUBW | ANDW | ORW | XORW | SHLW | SARW | SHRW
132 :     | ADDB | SUBB | ANDB | ORB | XORB | SHLB | SARB | SHRB
133 :    
134 : leunga 606 datatype multDivOp! = MULL | IDIVL | DIVL
135 : monnier 409
136 : george 545 datatype unaryOp! = DECL | INCL | NEGL | NOTL | NOTW | NOTB
137 : monnier 409
138 : george 545 datatype move! = MOVL
139 :     | MOVB
140 :     | MOVW
141 :     | MOVSWL | MOVZWL (* word -> long *)
142 :     | MOVSBL | MOVZBL (* byte -> long *)
143 : monnier 409
144 :     (* The Intel manual is incorrect on the description of FDIV and FDIVR *)
145 :     datatype fbinOp! =
146 : leunga 565 FADDP | FADDS
147 :     | FMULP | FMULS
148 :     | FCOMS
149 :     | FCOMPS
150 :     | FSUBP | FSUBS (* ST(1) := ST-ST(1); [pop] *)
151 :     | FSUBRP | FSUBRS (* ST(1) := ST(1)-ST; [pop] *)
152 :     | FDIVP | FDIVS (* ST(1) := ST/ST(1); [pop] *)
153 :     | FDIVRP | FDIVRS (* ST(1) := ST(1)/ST; [pop] *)
154 :     | FADDL
155 :     | FMULL
156 :     | FCOML
157 :     | FCOMPL
158 :     | FSUBL (* ST(1) := ST-ST(1); [pop] *)
159 :     | FSUBRL (* ST(1) := ST(1)-ST; [pop] *)
160 :     | FDIVL (* ST(1) := ST/ST(1); [pop] *)
161 :     | FDIVRL (* ST(1) := ST(1)/ST; [pop] *)
162 : monnier 409
163 : leunga 565 datatype fibinOp! =
164 :     FIADDS | FIMULS | FICOMS | FICOMPS
165 :     | FISUBS | FISUBRS | FIDIVS | FIDIVRS
166 :     | FIADDL | FIMULL | FICOML | FICOMPL
167 :     | FISUBL | FISUBRL | FIDIVL | FIDIVRL
168 :    
169 : monnier 409 datatype funOp! = FABS | FCHS
170 : george 545 | FSIN | FCOS | FTAN
171 :     | FSCALE | FRNDINT | FSQRT
172 :     | FTST | FXAM
173 :     | FINCSTP | FDECSTP
174 : monnier 409
175 : george 545 datatype fenvOp! = FLDENV | FNLDENV | FSTENV | FNSTENV
176 :    
177 : monnier 409 end (* struct Instruction *)
178 :    
179 : leunga 583 (*
180 :     * Instruction encoding on the x86
181 :     * Because of variable width instructions.
182 :     * We decompose each byte field into a seperate format first, then combine
183 :     * then to form the real instructions
184 :     *)
185 :     instruction formats 8 bits
186 :     modrm{mod:2, reg:3, rm:3}
187 :     | sib{ss:2, index:3, base:3}
188 :     | immed8{imm:8}
189 :    
190 :     instruction formats 32 bits
191 :     immed32{imm:32}
192 :    
193 : monnier 409 (* A bunch of routines for emitting assembly *)
194 :     functor Assembly
195 :     (structure MemRegs : MEMORY_REGISTERS where I = Instr) =
196 :     struct
197 :     val memReg = MemRegs.memReg regmap
198 : monnier 429 fun emitInt32 i =
199 :     let val s = Int32.toString i
200 :     val s = if i >= 0 then s else "-"^String.substring(s,1,size s-1)
201 :     in emit s end
202 :    
203 : monnier 409 fun emitScale 0 = emit "1"
204 :     | emitScale 1 = emit "2"
205 :     | emitScale 2 = emit "4"
206 :     | emitScale 3 = emit "8"
207 :     | emitScale _ = error "emitScale"
208 :    
209 :     and eImmed(I.Immed (i)) = emitInt32 i
210 :     | eImmed(I.ImmedLabel lexp) = emit_labexp lexp
211 :     | eImmed _ = error "eImmed"
212 :    
213 :     and emit_operand opn =
214 :     case opn of
215 :     I.Immed i => (emit "$"; emitInt32 i)
216 :     | I.ImmedLabel lexp => (emit "$"; emit_labexp lexp)
217 :     | I.LabelEA le => emit_labexp le
218 :     | I.Relative _ => error "emit_operand"
219 :     | I.Direct r => emit_GP r
220 : monnier 498 | I.MemReg r => emit_operand(memReg opn)
221 : george 555 | I.ST f => emit_FP f
222 :     | I.FDirect f => emit_operand(memReg opn)
223 : monnier 409 | I.Displace{base,disp,mem,...} =>
224 : george 545 (emit_disp disp; emit "("; emit_GP base; emit ")";
225 : monnier 409 emit_region mem)
226 : leunga 576 | I.Indexed{base,index,scale,disp,mem,...} =>
227 :     (emit_disp disp; emit "(";
228 :     case base of
229 :     NONE => ()
230 :     | SOME base => emit_GP base;
231 :     comma();
232 :     emit_GP index; comma();
233 : george 545 emitScale scale; emit ")"; emit_region mem)
234 : monnier 409
235 : george 545 and emit_disp(I.Immed 0) = ()
236 :     | emit_disp(I.Immed i) = emitInt32 i
237 :     | emit_disp(I.ImmedLabel lexp) = emit_labexp lexp
238 :     | emit_disp _ = error "emit_disp"
239 :    
240 : monnier 409 (* The gas assembler does not like the "$" prefix for immediate
241 :     * labels in certain instructions.
242 :     *)
243 :     fun stupidGas(I.ImmedLabel lexp) = emit_labexp lexp
244 : leunga 594 | stupidGas opnd = (emit "*"; emit_operand opnd)
245 : monnier 409
246 : george 555 (* Display the floating point binary opcode *)
247 :     fun isMemOpnd(I.MemReg _) = true
248 :     | isMemOpnd(I.FDirect f) = true
249 :     | isMemOpnd(I.LabelEA _) = true
250 :     | isMemOpnd(I.Displace _) = true
251 :     | isMemOpnd(I.Indexed _) = true
252 :     | isMemOpnd _ = false
253 : leunga 565 fun chop fbinOp =
254 : george 555 let val n = size fbinOp
255 : leunga 565 in case Char.toLower(String.sub(fbinOp,n-1)) of
256 :     (#"s" | #"l") => String.substring(fbinOp,0,n-1)
257 : george 555 | _ => fbinOp
258 : leunga 565 end
259 : george 555
260 : monnier 409 val emit_dst = emit_operand
261 :     val emit_src = emit_operand
262 :     val emit_opnd = emit_operand
263 :     val emit_rsrc = emit_operand
264 :     val emit_lsrc = emit_operand
265 :     val emit_addr = emit_operand
266 : george 545 val emit_src1 = emit_operand
267 :     end (* Instruction *)
268 : monnier 409
269 :     (* many of these instructions imply certain register usages *)
270 :     instruction
271 :     NOP
272 :     ``nop''
273 :    
274 :     | JMP of operand * Label.label list
275 :     ``jmp\t<stupidGas operand>''
276 :    
277 :     | JCC of {cond:cond, opnd:operand}
278 : george 545 ``j<cond>\t<stupidGas opnd>''
279 : monnier 409
280 :     | CALL of operand * C.cellset * C.cellset * Region.region
281 : monnier 498 ``call\t<stupidGas operand><region><
282 :     emit_defs(cellset1)><
283 :     emit_uses(cellset2)>''
284 : monnier 409
285 : leunga 594 | ENTER of {src1:operand, src2:operand}
286 :     ``enter\t<emit_operand src1>, <emit_operand src2>''
287 : leunga 593
288 : george 545 | LEAVE
289 :     ``leave''
290 :    
291 : monnier 429 | RET of operand option
292 :     ``ret<case operand of NONE => ()
293 :     | SOME e => (emit "\t"; emit_operand e)>''
294 : monnier 409
295 :     (* integer *)
296 :     | MOVE of {mvOp:move, src:operand, dst:operand}
297 :     ``<mvOp>\t<src>, <dst>''
298 :    
299 :     | LEA of {r32: $GP, addr: operand}
300 :     ``leal\t<addr>, <r32>''
301 :    
302 : george 545 | CMPL of {lsrc: operand, rsrc: operand}
303 : monnier 409 ``cmpl\t<rsrc>, <lsrc>''
304 :    
305 : george 545 | CMPW of {lsrc: operand, rsrc: operand}
306 :     ``cmpb\t<rsrc>, <lsrc>''
307 :    
308 :     | CMPB of {lsrc: operand, rsrc: operand}
309 :     ``cmpb\t<rsrc>, <lsrc>''
310 :    
311 :     | TESTL of {lsrc: operand, rsrc: operand}
312 :     ``testl\t<rsrc>, <lsrc>''
313 :    
314 :     | TESTW of {lsrc: operand, rsrc: operand}
315 :     ``testw\t<rsrc>, <lsrc>''
316 :    
317 :     | TESTB of {lsrc: operand, rsrc: operand}
318 :     ``testb\t<rsrc>, <lsrc>''
319 :    
320 : monnier 409 | BINARY of {binOp:binaryOp, src:operand, dst:operand}
321 : george 545 asm: (case (src,binOp) of
322 :     (I.Direct _,
323 :     (I.SARL | I.SHRL | I.SHLL |
324 :     I.SARW | I.SHRW | I.SHLW |
325 :     I.SARB | I.SHRB | I.SHLB)) => ``<binOp>\t%cl, <dst>''
326 :     | _ => ``<binOp>\t<src>, <dst>''
327 :     )
328 : monnier 409
329 :     | MULTDIV of {multDivOp:multDivOp, src:operand}
330 : leunga 606 ``<multDivOp>\t<src>''
331 : monnier 409
332 : george 545 | MUL3 of {dst: $GP, src2: Int32.int option, src1:operand}
333 :     (* Fermin: constant operand must go first *)
334 :     asm: (case src2 of
335 :     NONE => ``imul\t<src1>, <dst>''
336 :     | SOME i => ``imul\t$<emitInt32 i>, <src1>, <dst>''
337 :     )
338 : monnier 409
339 :     | UNARY of {unOp:unaryOp, opnd:operand}
340 : george 545 ``<unOp>\t<opnd>''
341 : monnier 409
342 : george 545 (* set byte on condition code; note that
343 :     * this only sets the low order byte, so it also
344 :     * uses its operand.
345 :     *)
346 :     | SET of {cond:cond, opnd:operand}
347 :     ``set<cond>\t<opnd>''
348 :    
349 :     (* conditional move; Pentium Pro or higher only
350 :     * Destination must be a register.
351 :     *)
352 :     | CMOV of {cond:cond, src:operand, dst: $GP}
353 :     ``cmov<cond>\t<src>, <dst>''
354 :    
355 :     | PUSHL of operand
356 : monnier 409 ``pushl\t<operand>''
357 :    
358 : george 545 | PUSHW of operand
359 :     ``pushw\t<operand>''
360 :    
361 :     | PUSHB of operand
362 :     ``pushb\t<operand>''
363 :    
364 : monnier 409 | POP of operand
365 :     ``popl\t<operand>''
366 :    
367 :     | CDQ
368 :     ``cdq''
369 :    
370 :     | INTO
371 :     ``into''
372 :    
373 :     (* parallel copies *)
374 :     | COPY of {dst: $GP list, src: $GP list, tmp:operand option}
375 : george 545 asm: emitInstrs (Shuffle.shuffle{regmap,tmp,dst,src})
376 :    
377 : monnier 409 | FCOPY of {dst: $FP list, src: $FP list, tmp:operand option}
378 : george 545 asm: emitInstrs (Shuffle.shufflefp{regmap,tmp,dst,src})
379 : monnier 409
380 :     (* floating *)
381 :     | FBINARY of {binOp:fbinOp, src:operand, dst:operand}
382 : leunga 565 asm: (if isMemOpnd src then ``<binOp>\t<src>''
383 :     else ``<emit(chop(asm_fbinOp binOp))>\t<src>, <dst>''
384 :     )
385 : monnier 409
386 : leunga 565 | FIBINARY of {binOp:fibinOp, src:operand}
387 :     asm: ``<binOp>\t<src>'' (* the implied destination is %ST(0) *)
388 :    
389 : monnier 409 | FUNARY of funOp
390 :     ``<funOp>''
391 :    
392 :     | FUCOMPP
393 :     ``fucompp''
394 :    
395 : george 545 | FCOMPP
396 :     ``fcompp''
397 : monnier 409
398 : george 545 | FXCH of {opnd: $FP}
399 :     asm: (``fxch\t''; if opnd = C.ST(1) then () else ``<opnd>'')
400 : monnier 409
401 : george 545 | FSTPL of operand
402 :     ``fstpl\t<operand>''
403 :    
404 :     | FSTPS of operand
405 :     ``fstps\t<operand>''
406 :    
407 : george 555 | FSTPT of operand
408 :     ``fstps\t<operand>''
409 :    
410 : leunga 579 | FSTL of operand
411 :     ``fstl\t<operand>''
412 :    
413 :     | FSTS of operand
414 :     ``fsts\t<operand>''
415 :    
416 : leunga 565 | FLD1
417 :     ``fld1''
418 :    
419 :     | FLDL2E
420 :     ``fldl2e''
421 :    
422 :     | FLDL2T
423 :     ``fldl2t''
424 :    
425 :     | FLDLG2
426 :     ``fldlg2''
427 :    
428 :     | FLDLN2
429 :     ``fldln2''
430 :    
431 :     | FLDPI
432 :     ``fldpi''
433 :    
434 :     | FLDZ
435 :     ``fldz''
436 :    
437 : george 545 | FLDL of operand
438 :     ``fldl\t<operand>''
439 :    
440 :     | FLDS of operand
441 :     ``flds\t<operand>''
442 :    
443 : george 555 | FLDT of operand
444 :     ``fldt\t<operand>''
445 :    
446 : monnier 409 | FILD of operand
447 :     ``fild\t<operand>''
448 :    
449 : leunga 565 | FILDL of operand
450 :     ``fildl\t<operand>''
451 :    
452 :     | FILDLL of operand
453 :     ``fildll\t<operand>''
454 :    
455 : monnier 409 | FNSTSW
456 :     ``fnstsw''
457 :    
458 : george 545 | FENV of {fenvOp:fenvOp, opnd:operand} (* load/store environment *)
459 :     ``<fenvOp>\t<opnd>''
460 :    
461 : monnier 409 (* misc *)
462 :     | SAHF
463 :     ``sahf''
464 :    
465 :     (* annotations *)
466 :     | ANNOTATION of {i:instruction, a:Annotations.annotation}
467 : leunga 624 asm: (comment(Annotations.toString a); nl(); emitInstr i)
468 :    
469 :     | SOURCE of {}
470 :     asm: ``source''
471 :     mc: ()
472 :    
473 :     | SINK of {}
474 :     asm: ``sink''
475 :     mc: ()
476 :    
477 :     | PHI of {}
478 :     asm: ``phi''
479 :     mc: ()
480 :    
481 : monnier 409 end
482 :    

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