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[smlnj] Diff of /sml/trunk/src/MLRISC/x86/x86.md
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Diff of /sml/trunk/src/MLRISC/x86/x86.md

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sml/branches/SMLNJ/src/MLRISC/x86/x86.md revision 410, Fri Sep 3 00:25:03 1999 UTC sml/trunk/src/MLRISC/x86/x86.md revision 545, Thu Feb 24 13:56:44 2000 UTC
# Line 27  Line 27 
27       *)       *)
28    
29     storage     storage
30        GP = 32 cells of 32 bits in cellset called "register"        GP "r" = 32 cells of 32 bits in cellset called "register"
31             assembly as             assembly as
32                      (fn 0 => "%eax"                      (fn (0,8)  => "%al"
33                        | 1 => "%ecx"                        | (0,16) => "%ax"
34                        | 2 => "%edx"                        | (0,32) => "%eax"
35                        | 3 => "%ebx"                        | (1,8)  => "%cl"
36                        | 4 => "%esp"                        | (1,16) => "%cx"
37                        | 5 => "%ebp"                        | (1,32) => "%ecx"
38                        | 6 => "%esi"                        | (2,8)  => "%dl"
39                        | 7 => "%edi"                        | (2,16) => "%dx"
40                        | r => "%"^Int.toString r                        | (2,32) => "%edx"
41                          | (3,8)  => "%bl"
42                          | (3,16) => "%bx"
43                          | (3,32) => "%ebx"
44                          | (4,16) => "%sp"
45                          | (4,32) => "%esp"
46                          | (5,16) => "%bp"
47                          | (5,32) => "%ebp"
48                          | (6,16) => "%si"
49                          | (6,32) => "%esi"
50                          | (7,16) => "%di"
51                          | (7,32) => "%edi"
52                          | (r,_) => "%"^Int.toString r
53                      )                      )
54     |  FP = 32 cells of 80 bits in cellset called "floating point register"     |  FP "f" = 32 cells of 80 bits in cellset called "floating point register"
55             assembly as (fn f => if f >= 0 andalso f < 8                 assembly as (fn (f,_) =>
56                                  then "%st("^Int.toString f^")"                                      if f = 0 then "%st"
57                                  else "%f"^Int.toString f (* fake register *)                                      else if f < 8 then "%st("^Int.toString f^")"
58                                        else "%f"^Int.toString f
59                                            (* pseudo register *)
60                         )                         )
61     |  CC = cells of 32 bits in cellset called "condition code register"     |  CC "cc" = cells of 32 bits in cellset called "condition code register"
62             assembly as "cc"             assembly as "cc"
63       |  MEM "m" = cells of 8 bits called "memory"
64                    assembly as (fn (r,_) => "m"^Int.toString r)
65       |  CTRL "ctrl" = cells of 8 bits called "control"
66                    assembly as (fn (r,_) => "ctrl"^Int.toString r)
67    
68     locations     locations
69         eax     = $GP[0]         eax     = $GP[0]
70     and ecx     = $GP[1]     and ecx     = $GP[1]
# Line 55  Line 74 
74     and ebp     = $GP[5]     and ebp     = $GP[5]
75     and esi     = $GP[6]     and esi     = $GP[6]
76     and edi     = $GP[7]     and edi     = $GP[7]
77     and stackptrR = esp     and stackptrR = $GP[4]
78       and ST(x)   = $FP[x]
79     and asmTmpR   = ~1 (* not used *)     and asmTmpR   = ~1 (* not used *)
80     and fasmTmp   = ~1 (* not used *)     and fasmTmp   = ~1 (* not used *)
81    
82     structure Cells =     structure RTL =
83     struct     struct
       fun zeroReg _ = NONE  
84     end     end
85    
   
    (*  
    semantics X86 =  
    struct  
       include "MD++/basis.md"  
       open Basis  
       structure Int32 = struct type int end  
       type 'a option  
    end *)  
   
86     structure Instruction = struct     structure Instruction = struct
87   (* An effective address can be any combination of   (* An effective address can be any combination of
88    *  base + index*scale + disp    *  base + index*scale + disp
# Line 96  Line 105 
105    (* Note: Relative is only generated after sdi resolution *)    (* Note: Relative is only generated after sdi resolution *)
106    datatype operand =    datatype operand =
107       Immed      of Int32.int       Immed      of Int32.int
    | Const      of Constant.const  
108     | ImmedLabel of LabelExp.labexp     | ImmedLabel of LabelExp.labexp
109     | Relative   of int     | Relative   of int
110     | LabelEA    of LabelExp.labexp     | LabelEA    of LabelExp.labexp
111     | Direct     of $GP     | Direct     of $GP
112     | FDirect    of $FP     | FDirect    of $FP
113       | MemReg     of int (* pseudo memory register *)
114     | Displace   of {base: $GP, disp:operand, mem:Region.region}     | Displace   of {base: $GP, disp:operand, mem:Region.region}
115     | Indexed    of {base: $GP option, index: $GP, scale:int, disp:operand,     | Indexed    of {base: $GP option, index: $GP, scale:int, disp:operand,
116                      mem:Region.region}                      mem:Region.region}
117    
118    type ea = operand    type addressing_mode = operand
   
   datatype binaryOp! = ADD | SUB  | AND | OR | XOR | SHL | SAR | SHR  
119    
120    datatype multDivOp! = UMUL | IDIV | UDIV    type ea = operand
   
   datatype unaryOp! = DEC | INC | NEG | NOT  
   
   datatype move! = MOVL | MOVZX | MOVB  
121    
122    datatype cond! =    datatype cond! =
123        EQ | NE | LT | LE | GT | GE        EQ "e" | NE | LT "l" | LE | GT "g" | GE
124      | B  | BE (* below *)   | A  | AE (* above *)      | B  | BE (* below *)   | A  | AE (* above *)
125      | C  | NC (* if carry *)| P  | NP (* if parity *)      | C  | NC (* if carry *)| P  | NP (* if parity *)
126      | O  | NO (* overflow *)      | O  | NO (* overflow *)
127    
128      datatype binaryOp! =
129         ADDL | SUBL | ANDL | ORL | XORL | SHLL | SARL | SHRL | ADCL | SBBL
130       | ADDW | SUBW | ANDW | ORW | XORW | SHLW | SARW | SHRW
131       | ADDB | SUBB | ANDB | ORB | XORB | SHLB | SARB | SHRB
132    
133      datatype multDivOp! = UMUL | IDIV | UDIV
134    
135      datatype unaryOp! = DECL | INCL | NEGL | NOTL | NOTW | NOTB
136    
137      datatype move! = MOVL
138                     | MOVB
139                     | MOVW
140                     | MOVSWL | MOVZWL  (* word -> long *)
141                     | MOVSBL | MOVZBL  (* byte -> long *)
142    
143   (* The Intel manual is incorrect on the description of FDIV and FDIVR *)   (* The Intel manual is incorrect on the description of FDIV and FDIVR *)
144    datatype fbinOp! =    datatype fbinOp! =
145        FADDP  | FADD        FADDP  | FADD  | FIADD
146      | FMULP  | FMUL      | FMULP  | FMUL  | FIMUL
147      | FSUBP  | FSUB             (* ST(1) := ST-ST(1); [pop] *)      | FSUBP  | FSUB  | FISUB    (* ST(1) := ST-ST(1); [pop] *)
148      | FSUBRP | FSUBR            (* ST(1) := ST(1)-ST; [pop] *)      | FSUBRP | FSUBR | FISUBR   (* ST(1) := ST(1)-ST; [pop] *)
149      | FDIVP  | FDIV             (* ST(1) := ST/ST(1); [pop] *)      | FDIVP  | FDIV  | FIDIV    (* ST(1) := ST/ST(1); [pop] *)
150      | FDIVRP | FDIVR            (* ST(1) := ST(1)/ST; [pop] *)      | FDIVRP | FDIVR | FIDIVR   (* ST(1) := ST(1)/ST; [pop] *)
151    
152    datatype funOp! = FABS | FCHS    datatype funOp! = FABS | FCHS
153                      | FSIN | FCOS | FTAN
154                      | FSCALE | FRNDINT | FSQRT
155                      | FTST | FXAM
156                      | FINCSTP | FDECSTP
157    
158      datatype fenvOp! = FLDENV | FNLDENV | FSTENV | FNSTENV
159    
160    end (* struct Instruction *)    end (* struct Instruction *)
161    
# Line 140  Line 164 
164       (structure MemRegs : MEMORY_REGISTERS where I = Instr) =       (structure MemRegs : MEMORY_REGISTERS where I = Instr) =
165    struct    struct
166       val memReg = MemRegs.memReg regmap       val memReg = MemRegs.memReg regmap
167       fun emitInt32 i = emit(if i < 0 then "-"^Int32.toString(~i)       fun emitInt32 i =
168                              else Int32.toString i)       let val s = Int32.toString i
169       fun emit_src2 NONE = ()           val s = if i >= 0 then s else "-"^String.substring(s,1,size s-1)
170         | emit_src2(SOME i) = (emit "$"; emitInt32 i; emit ", ")       in  emit s end
171    
172       fun emitScale 0 = emit "1"       fun emitScale 0 = emit "1"
173         | emitScale 1 = emit "2"         | emitScale 1 = emit "2"
# Line 152  Line 176 
176         | emitScale _ = error "emitScale"         | emitScale _ = error "emitScale"
177    
178       and eImmed(I.Immed (i)) = emitInt32 i       and eImmed(I.Immed (i)) = emitInt32 i
        | eImmed(I.Const c) = emit_const c  
179         | eImmed(I.ImmedLabel lexp) = emit_labexp lexp         | eImmed(I.ImmedLabel lexp) = emit_labexp lexp
180         | eImmed _ = error "eImmed"         | eImmed _ = error "eImmed"
181    
182       and emit_operand opn =       and emit_operand opn =
183           case opn of           case opn of
184           I.Immed i => (emit "$"; emitInt32 i)           I.Immed i => (emit "$"; emitInt32 i)
        | I.Const c => emit_const c  
185         | I.ImmedLabel lexp => (emit "$"; emit_labexp lexp)         | I.ImmedLabel lexp => (emit "$"; emit_labexp lexp)
186         | I.LabelEA le => emit_labexp le         | I.LabelEA le => emit_labexp le
187         | I.Relative _ => error "emit_operand"         | I.Relative _ => error "emit_operand"
188         | I.Direct r => emit_GP r         | I.Direct r => emit_GP r
189           | I.MemReg r => emit_operand(memReg opn)
190         | I.FDirect f =>         | I.FDirect f =>
191              let val f' = regmap f              let val f' = regmap f
192              in  if f' < (32+8) then emit_FP f' else emit_operand(memReg opn) end              in  if f' < (32+8) then emit_FP f' else emit_operand(memReg opn) end
        | I.Displace{base,disp=I.Immed(0),mem,...} =>  
            (emit "("; emit_GP base; emit ")"; emit_region mem)  
193         | I.Displace{base,disp,mem,...} =>         | I.Displace{base,disp,mem,...} =>
194             (eImmed disp; emit "("; emit_GP base; emit ")";             (emit_disp disp; emit "("; emit_GP base; emit ")";
195              emit_region mem)              emit_region mem)
196         | I.Indexed{base=NONE,index,scale,disp,mem,...} =>         | I.Indexed{base=NONE,index,scale,disp,mem,...} =>
197            (emit "("; emit_GP index; comma(); emitScale scale; emit ")";            (emit_disp disp; emit "("; emit_GP index; comma();
198             emit_region mem)             emitScale scale; emit ")"; emit_region mem)
199         | I.Indexed{base=SOME base,index,scale,disp,mem,...} =>         | I.Indexed{base=SOME base,index,scale,disp,mem,...} =>
200           (eOptionalDisp disp; emit "("; emit_GP base;           (emit_disp disp; emit "("; emit_GP base;
201            comma(); emit_GP index; emitScale scale; emit ")";            comma(); emit_GP index; comma(); emitScale scale; emit ")";
202            emit_region mem)            emit_region mem)
203        and eOptionalDisp(I.Immed 0) = ()  
204          | eOptionalDisp(I.Const c) = emit(Constant.toString c)        and emit_disp(I.Immed 0) = ()
205          | eOptionalDisp(I.Immed i) = emitInt32 i          | emit_disp(I.Immed i) = emitInt32 i
206          | eOptionalDisp _ = error "eOptionalDisp"          | emit_disp(I.ImmedLabel lexp) = emit_labexp lexp
207            | emit_disp _ = error "emit_disp"
208    
209       (* The gas assembler does not like the "$" prefix for immediate       (* The gas assembler does not like the "$" prefix for immediate
210        * labels in certain instructions.        * labels in certain instructions.
# Line 194  Line 216 
216        val emit_dst = emit_operand        val emit_dst = emit_operand
217        val emit_src = emit_operand        val emit_src = emit_operand
218        val emit_opnd = emit_operand        val emit_opnd = emit_operand
       val emit_src1 = emit_operand  
219        val emit_rsrc = emit_operand        val emit_rsrc = emit_operand
220        val emit_lsrc = emit_operand        val emit_lsrc = emit_operand
221        val emit_addr = emit_operand        val emit_addr = emit_operand
222    end        val emit_src1 = emit_operand
223      end (* Instruction *)
224    
225   (* many of these instructions imply certain register usages *)   (* many of these instructions imply certain register usages *)
226    instruction    instruction
# Line 209  Line 231 
231          ``jmp\t<stupidGas operand>''          ``jmp\t<stupidGas operand>''
232    
233      | JCC of {cond:cond, opnd:operand}      | JCC of {cond:cond, opnd:operand}
234          ``j<cond>, <stupidGas opnd>''          ``j<cond>\t<stupidGas opnd>''
235    
236      | CALL of operand * C.cellset * C.cellset * Region.region      | CALL of operand * C.cellset * C.cellset * Region.region
237          ``call\t<stupidGas operand><region>''          ``call\t<stupidGas operand><region><
238              emit_defs(cellset1)><
239      | RET            emit_uses(cellset2)>''
240          ``ret''  
241        | LEAVE
242            ``leave''
243    
244        | RET of operand option
245            ``ret<case operand of NONE => ()
246                                | SOME e => (emit "\t"; emit_operand e)>''
247    
248     (* integer *)     (* integer *)
249      | MOVE of {mvOp:move, src:operand, dst:operand}      | MOVE of {mvOp:move, src:operand, dst:operand}
# Line 224  Line 252 
252      | LEA of {r32: $GP, addr: operand}      | LEA of {r32: $GP, addr: operand}
253          ``leal\t<addr>, <r32>''          ``leal\t<addr>, <r32>''
254    
255      | CMP of {lsrc: operand, rsrc: operand}      | CMPL of {lsrc: operand, rsrc: operand}
256          ``cmpl\t<rsrc>, <lsrc>''          ``cmpl\t<rsrc>, <lsrc>''
257    
258        | CMPW of {lsrc: operand, rsrc: operand}
259            ``cmpb\t<rsrc>, <lsrc>''
260    
261        | CMPB of {lsrc: operand, rsrc: operand}
262            ``cmpb\t<rsrc>, <lsrc>''
263    
264        | TESTL of {lsrc: operand, rsrc: operand}
265            ``testl\t<rsrc>, <lsrc>''
266    
267        | TESTW of {lsrc: operand, rsrc: operand}
268            ``testw\t<rsrc>, <lsrc>''
269    
270        | TESTB of {lsrc: operand, rsrc: operand}
271            ``testb\t<rsrc>, <lsrc>''
272    
273      | BINARY of {binOp:binaryOp, src:operand, dst:operand}      | BINARY of {binOp:binaryOp, src:operand, dst:operand}
274          ``<binOp>l\t<src>, <dst>''          asm: (case (src,binOp) of
275                   (I.Direct _,
276                   (I.SARL | I.SHRL | I.SHLL |
277                    I.SARW | I.SHRW | I.SHLW |
278                    I.SARB | I.SHRB | I.SHLB)) => ``<binOp>\t%cl, <dst>''
279                 | _ => ``<binOp>\t<src>, <dst>''
280                 )
281    
282      | MULTDIV of {multDivOp:multDivOp, src:operand}      | MULTDIV of {multDivOp:multDivOp, src:operand}
283          ``<multDivOp>l\t<src>''          ``<multDivOp>l\t<src>''
284    
285      | MUL3 of {dst:int, src1:operand, src2: Int32.int option}      | MUL3 of {dst: $GP, src2: Int32.int option, src1:operand}
286          ``imul\t<src1>, <emit_src2 src2><dst>''          (* Fermin: constant operand must go first *)
287            asm: (case src2 of
288                    NONE => ``imul\t<src1>, <dst>''
289                  | SOME i => ``imul\t$<emitInt32 i>, <src1>, <dst>''
290                 )
291    
292      | UNARY of {unOp:unaryOp, opnd:operand}      | UNARY of {unOp:unaryOp, opnd:operand}
293          ``<unOp>l\t<opnd>''          ``<unOp>\t<opnd>''
294    
295          (* set byte on condition code; note that
296           * this only sets the low order byte, so it also
297           * uses its operand.
298           *)
299        | SET of {cond:cond, opnd:operand}
300             ``set<cond>\t<opnd>''
301    
302            (* conditional move; Pentium Pro or higher only
303             * Destination must be a register.
304             *)
305        | CMOV of {cond:cond, src:operand, dst: $GP}
306            ``cmov<cond>\t<src>, <dst>''
307    
308      | PUSH of operand      | PUSHL of operand
309          ``pushl\t<operand>''          ``pushl\t<operand>''
310    
311        | PUSHW of operand
312            ``pushw\t<operand>''
313    
314        | PUSHB of operand
315            ``pushb\t<operand>''
316    
317      | POP of operand      | POP of operand
318          ``popl\t<operand>''          ``popl\t<operand>''
319    
# Line 253  Line 325 
325    
326     (* parallel copies *)     (* parallel copies *)
327      | COPY of {dst: $GP list, src: $GP list, tmp:operand option}      | COPY of {dst: $GP list, src: $GP list, tmp:operand option}
328          ``<emitInstrs (Shuffle.shuffle{regmap,tmp,dst,src})>''          asm: emitInstrs (Shuffle.shuffle{regmap,tmp,dst,src})
     | FCOPY of {dst: $FP list, src: $FP list, tmp:operand option}  
         ``<emitInstrs (Shuffle.shufflefp{regmap,tmp,dst,src})>''  
329    
330        | FCOPY of {dst: $FP list, src: $FP list, tmp:operand option}
331            asm: emitInstrs (Shuffle.shufflefp{regmap,tmp,dst,src})
332    
333     (* floating *)     (* floating *)
334      | FBINARY of {binOp:fbinOp, src:operand, dst:operand}      | FBINARY of {binOp:fbinOp, src:operand, dst:operand}
# Line 268  Line 340 
340      | FUCOMPP      | FUCOMPP
341          ``fucompp''          ``fucompp''
342    
343      | FXCH      | FCOM
344          ``fxch''          ``fcom''
345    
346        | FCOMPP
347            ``fcompp''
348    
349        | FXCH of {opnd: $FP}
350            asm: (``fxch\t''; if opnd = C.ST(1) then () else ``<opnd>'')
351    
352      | FSTP of operand      | FSTPL of operand
353          ``fstp\t<operand>''          ``fstpl\t<operand>''
354    
355      | FLD of operand      | FSTPS of operand
356          ``fld\t<operand>''          ``fstps\t<operand>''
357    
358        | FLDL of operand
359            ``fldl\t<operand>''
360    
361        | FLDS of operand
362            ``flds\t<operand>''
363    
364      | FILD of operand      | FILD of operand
365          ``fild\t<operand>''          ``fild\t<operand>''
# Line 283  Line 367 
367      | FNSTSW      | FNSTSW
368          ``fnstsw''          ``fnstsw''
369    
370        | FENV of {fenvOp:fenvOp, opnd:operand} (* load/store environment *)
371            ``<fenvOp>\t<opnd>''
372    
373     (* misc *)     (* misc *)
374      | SAHF      | SAHF
375          ``sahf''          ``sahf''
376    
377     (* annotations *)     (* annotations *)
378      | ANNOTATION of {i:instruction, a:Annotations.annotation}      | ANNOTATION of {i:instruction, a:Annotations.annotation}
379          ``<(emitInstr i; comment(Annotations.toString a))>''          asm: (emitInstr i; comment(Annotations.toString a))
   
     | GROUP of Annotations.annotation  
         ``<comment(Annotations.toString annotation)>''  
   
380  end  end
381    

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