Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /sml/trunk/src/MLRISC/x86/x86.md
ViewVC logotype

Diff of /sml/trunk/src/MLRISC/x86/x86.md

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 545, Thu Feb 24 13:56:44 2000 UTC revision 583, Thu Mar 23 21:52:30 2000 UTC
# Line 52  Line 52 
52                        | (r,_) => "%"^Int.toString r                        | (r,_) => "%"^Int.toString r
53                      )                      )
54     |  FP "f" = 32 cells of 80 bits in cellset called "floating point register"     |  FP "f" = 32 cells of 80 bits in cellset called "floating point register"
55                 assembly as (fn (f,_) =>                 assembly as (fn (0,_) => "%st"
56                                      if f = 0 then "%st"                               | (f,_) =>
57                                      else if f < 8 then "%st("^Int.toString f^")"                                  if f < 8 then "%st("^Int.toString f^")"
58                                      else "%f"^Int.toString f                                      else "%f"^Int.toString f
59                                          (* pseudo register *)                                          (* pseudo register *)
60                             )                             )
# Line 110  Line 110 
110     | LabelEA    of LabelExp.labexp     | LabelEA    of LabelExp.labexp
111     | Direct     of $GP     | Direct     of $GP
112     | FDirect    of $FP     | FDirect    of $FP
113       | ST         of $FP
114     | MemReg     of int (* pseudo memory register *)     | MemReg     of int (* pseudo memory register *)
115     | Displace   of {base: $GP, disp:operand, mem:Region.region}     | Displace   of {base: $GP, disp:operand, mem:Region.region}
116     | Indexed    of {base: $GP option, index: $GP, scale:int, disp:operand,     | Indexed    of {base: $GP option, index: $GP, scale:int, disp:operand,
# Line 142  Line 143 
143    
144   (* The Intel manual is incorrect on the description of FDIV and FDIVR *)   (* The Intel manual is incorrect on the description of FDIV and FDIVR *)
145    datatype fbinOp! =    datatype fbinOp! =
146        FADDP  | FADD  | FIADD        FADDP   | FADDS
147      | FMULP  | FMUL  | FIMUL      | FMULP   | FMULS
148      | FSUBP  | FSUB  | FISUB    (* ST(1) := ST-ST(1); [pop] *)                | FCOMS
149      | FSUBRP | FSUBR | FISUBR   (* ST(1) := ST(1)-ST; [pop] *)                | FCOMPS
150      | FDIVP  | FDIV  | FIDIV    (* ST(1) := ST/ST(1); [pop] *)      | FSUBP   | FSUBS   (* ST(1) := ST-ST(1); [pop] *)
151      | FDIVRP | FDIVR | FIDIVR   (* ST(1) := ST(1)/ST; [pop] *)      | FSUBRP  | FSUBRS  (* ST(1) := ST(1)-ST; [pop] *)
152        | FDIVP   | FDIVS   (* ST(1) := ST/ST(1); [pop] *)
153        | FDIVRP  | FDIVRS  (* ST(1) := ST(1)/ST; [pop] *)
154                  | FADDL
155                  | FMULL
156                  | FCOML
157                  | FCOMPL
158                  | FSUBL   (* ST(1) := ST-ST(1); [pop] *)
159                  | FSUBRL  (* ST(1) := ST(1)-ST; [pop] *)
160                  | FDIVL   (* ST(1) := ST/ST(1); [pop] *)
161                  | FDIVRL  (* ST(1) := ST(1)/ST; [pop] *)
162    
163      datatype fibinOp! =
164          FIADDS | FIMULS   | FICOMS | FICOMPS
165        | FISUBS | FISUBRS  | FIDIVS | FIDIVRS
166        | FIADDL | FIMULL   | FICOML | FICOMPL
167        | FISUBL | FISUBRL  | FIDIVL | FIDIVRL
168    
169    datatype funOp! = FABS | FCHS    datatype funOp! = FABS | FCHS
170                    | FSIN | FCOS | FTAN                    | FSIN | FCOS | FTAN
# Line 159  Line 176 
176    
177    end (* struct Instruction *)    end (* struct Instruction *)
178    
179      (*
180       * Instruction encoding on the x86
181       * Because of variable width instructions.
182       * We decompose each byte field into a seperate format first, then combine
183       * then to form the real instructions
184       *)
185      instruction formats 8 bits
186        modrm{mod:2, reg:3, rm:3}
187      | sib{ss:2, index:3, base:3}
188      | immed8{imm:8}
189    
190      instruction formats 32 bits
191        immed32{imm:32}
192    
193    (* A bunch of routines for emitting assembly *)    (* A bunch of routines for emitting assembly *)
194    functor Assembly    functor Assembly
195       (structure MemRegs : MEMORY_REGISTERS where I = Instr) =       (structure MemRegs : MEMORY_REGISTERS where I = Instr) =
# Line 187  Line 218 
218         | I.Relative _ => error "emit_operand"         | I.Relative _ => error "emit_operand"
219         | I.Direct r => emit_GP r         | I.Direct r => emit_GP r
220         | I.MemReg r => emit_operand(memReg opn)         | I.MemReg r => emit_operand(memReg opn)
221         | I.FDirect f =>         | I.ST f => emit_FP f
222              let val f' = regmap f         | I.FDirect f => emit_operand(memReg opn)
             in  if f' < (32+8) then emit_FP f' else emit_operand(memReg opn) end  
223         | I.Displace{base,disp,mem,...} =>         | I.Displace{base,disp,mem,...} =>
224             (emit_disp disp; emit "("; emit_GP base; emit ")";             (emit_disp disp; emit "("; emit_GP base; emit ")";
225              emit_region mem)              emit_region mem)
226         | I.Indexed{base=NONE,index,scale,disp,mem,...} =>         | I.Indexed{base,index,scale,disp,mem,...} =>
227            (emit_disp disp; emit "("; emit_GP index; comma();            (emit_disp disp; emit "(";
228               case base of
229                 NONE => ()
230               | SOME base => emit_GP base;
231               comma();
232               emit_GP index; comma();
233             emitScale scale; emit ")"; emit_region mem)             emitScale scale; emit ")"; emit_region mem)
        | I.Indexed{base=SOME base,index,scale,disp,mem,...} =>  
          (emit_disp disp; emit "("; emit_GP base;  
           comma(); emit_GP index; comma(); emitScale scale; emit ")";  
           emit_region mem)  
234    
235        and emit_disp(I.Immed 0) = ()        and emit_disp(I.Immed 0) = ()
236          | emit_disp(I.Immed i) = emitInt32 i          | emit_disp(I.Immed i) = emitInt32 i
# Line 213  Line 244 
244          | stupidGas(I.LabelEA _) = error "stupidGas"          | stupidGas(I.LabelEA _) = error "stupidGas"
245          | stupidGas opnd = emit_operand opnd          | stupidGas opnd = emit_operand opnd
246    
247         (* Display the floating point binary opcode *)
248          fun isMemOpnd(I.MemReg _) = true
249            | isMemOpnd(I.FDirect f) = true
250            | isMemOpnd(I.LabelEA _) = true
251            | isMemOpnd(I.Displace _) = true
252            | isMemOpnd(I.Indexed _) = true
253            | isMemOpnd _ = false
254          fun chop fbinOp =
255              let val n = size fbinOp
256              in  case Char.toLower(String.sub(fbinOp,n-1)) of
257                    (#"s" | #"l") => String.substring(fbinOp,0,n-1)
258                  | _ => fbinOp
259              end
260    
261        val emit_dst = emit_operand        val emit_dst = emit_operand
262        val emit_src = emit_operand        val emit_src = emit_operand
263        val emit_opnd = emit_operand        val emit_opnd = emit_operand
# Line 332  Line 377 
377    
378     (* floating *)     (* floating *)
379      | FBINARY of {binOp:fbinOp, src:operand, dst:operand}      | FBINARY of {binOp:fbinOp, src:operand, dst:operand}
380          ``<binOp>\t<src>, <dst>''          asm: (if isMemOpnd src then ``<binOp>\t<src>''
381                  else ``<emit(chop(asm_fbinOp binOp))>\t<src>, <dst>''
382                 )
383    
384        | FIBINARY of {binOp:fibinOp, src:operand}
385            asm: ``<binOp>\t<src>'' (* the implied destination is %ST(0) *)
386    
387      | FUNARY of funOp      | FUNARY of funOp
388          ``<funOp>''          ``<funOp>''
# Line 340  Line 390 
390      | FUCOMPP      | FUCOMPP
391          ``fucompp''          ``fucompp''
392    
     | FCOM  
         ``fcom''  
   
393      | FCOMPP      | FCOMPP
394          ``fcompp''          ``fcompp''
395    
# Line 355  Line 402 
402      | FSTPS of operand      | FSTPS of operand
403          ``fstps\t<operand>''          ``fstps\t<operand>''
404    
405        | FSTPT of operand
406            ``fstps\t<operand>''
407    
408        | FSTL of operand
409            ``fstl\t<operand>''
410    
411        | FSTS of operand
412            ``fsts\t<operand>''
413    
414        | FLD1
415            ``fld1''
416    
417        | FLDL2E
418            ``fldl2e''
419    
420        | FLDL2T
421            ``fldl2t''
422    
423        | FLDLG2
424            ``fldlg2''
425    
426        | FLDLN2
427            ``fldln2''
428    
429        | FLDPI
430            ``fldpi''
431    
432        | FLDZ
433            ``fldz''
434    
435      | FLDL of operand      | FLDL of operand
436          ``fldl\t<operand>''          ``fldl\t<operand>''
437    
438      | FLDS of operand      | FLDS of operand
439          ``flds\t<operand>''          ``flds\t<operand>''
440    
441        | FLDT of operand
442            ``fldt\t<operand>''
443    
444      | FILD of operand      | FILD of operand
445          ``fild\t<operand>''          ``fild\t<operand>''
446    
447        | FILDL of operand
448            ``fildl\t<operand>''
449    
450        | FILDLL of operand
451            ``fildll\t<operand>''
452    
453      | FNSTSW      | FNSTSW
454          ``fnstsw''          ``fnstsw''
455    

Legend:
Removed from v.545  
changed lines
  Added in v.583

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0