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[smlnj] Diff of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml
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Diff of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml

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revision 247, Sat Apr 17 18:47:13 1999 UTC revision 411, Fri Sep 3 00:25:03 1999 UTC
# Line 3  Line 3 
3   * COPYRIGHT (c) 1996 Bell Laboratories.   * COPYRIGHT (c) 1996 Bell Laboratories.
4   *   *
5   *)   *)
6  functor Alpha32CG(structure Emitter : EMITTER_NEW  functor Alpha32CG(structure Emitter : INSTRUCTION_EMITTER
7                      where I = Alpha32Instr                      where I = Alpha32Instr
8                      where P = Alpha32PseudoOps) : MACHINE_GEN =                      where P = Alpha32PseudoOps
9                        where S.B = Alpha32MLTree.BNames
10                      val alpha32x : bool (* the alpha32x backend or what? *)
11                     ) : MACHINE_GEN =
12  struct  struct
13    
14    structure I = Alpha32Instr    structure I = Alpha32Instr
15    structure C = Alpha32Cells    structure C = AlphaCells
16    structure R = Alpha32CpsRegs    structure R = Alpha32CpsRegs
17    structure B = Alpha32MLTree.BNames    structure B = Alpha32MLTree.BNames
18    structure F = Alpha32FlowGraph    structure F = Alpha32FlowGraph
# Line 22  Line 25 
25    
26    val stack = Alpha32Instr.Region.stack    val stack = Alpha32Instr.Region.stack
27    
28    structure Alpha32Rewrite = Alpha32Rewrite(Alpha32Instr)    structure Alpha32Rewrite = AlphaRewrite(Alpha32Instr)
29    
30    (* properties of instruction set *)    (* properties of instruction set *)
31    structure P =    structure P = AlphaProps(Alpha32Instr)
     Alpha32Props(structure Alpha32Instr= I  
                  structure Shuffle=Alpha32Shuffle)  
32    
33      structure FreqProps = FreqProps(P)
34    
35    (* Label backpatching and basic block scheduling *)    (* Label backpatching and basic block scheduling *)
36    structure BBSched =    structure BBSched =
37      BBSched2(structure Flowgraph = F      BBSched2(structure Flowgraph = F
38               structure Jumps =               structure Jumps =
39                 Alpha32Jumps(structure Instr=Alpha32Instr                 AlphaJumps(structure Instr=Alpha32Instr
40                              structure Shuffle=Alpha32Shuffle)                              structure Shuffle=Alpha32Shuffle)
41               structure Emitter = Emitter)               structure Emitter = Emitter)
42    
43    (* flow graph pretty printing routine *)    (* flow graph pretty printing routine *)
44      (*
45    structure PrintFlowGraph =    structure PrintFlowGraph =
46       PrintFlowGraphFn (structure FlowGraph = F       PrintFlowGraphFn (structure FlowGraph = F
47                         structure Emitter   = Asm)                         structure Emitter   = Asm)
48       *)
49    
50    val intSpillCnt = Ctrl.getInt "ra-int-spills"    val intSpillCnt = Ctrl.getInt "ra-int-spills"
51    val floatSpillCnt = Ctrl.getInt "ra-float-spills"    val floatSpillCnt = Ctrl.getInt "ra-float-spills"
# Line 155  Line 159 
159         regSpills := Intmap.new(8, RegSpills);         regSpills := Intmap.new(8, RegSpills);
160         fregSpills := Intmap.new(8, FregSpills))         fregSpills := Intmap.new(8, FregSpills))
161    
162      structure GR = GetReg(val nRegs=32 val available=R.availR)      structure GR = GetReg(val nRegs=32 val available=R.availR val first=0)
163      structure FR = GetReg(val nRegs=32 val available=R.availF)      structure FR = GetReg(val nRegs=32 val available=R.availF val first=32)
164    
165      structure Alpha32Ra =      structure Alpha32Ra =
166         Alpha32RegAlloc(structure P = P         AlphaRegAlloc(structure P = P
167                         structure I = Alpha32Instr                         structure I = Alpha32Instr
168                         structure F = F                         structure F = F
169                         structure Asm = Asm)                         structure Asm = Asm)
# Line 206  Line 210 
210      val fCopyProp = FloatRa.ra FloatRa.COPY_PROPAGATION []      val fCopyProp = FloatRa.ra FloatRa.COPY_PROPAGATION []
211    
212      fun ra cluster = let      fun ra cluster = let
213        val pg = PrintFlowGraph.printCluster TextIO.stdOut        (* val pg = PrintFlowGraph.printCluster TextIO.stdOut *)
214        fun intRa cluster = (GR.reset(); iRegAlloc cluster)        fun intRa cluster = (GR.reset(); iRegAlloc cluster)
215        fun floatRa cluster = (FR.reset(); fRegAlloc cluster)        fun floatRa cluster = (FR.reset(); fRegAlloc cluster)
216      in spillInit(); (floatRa o intRa) cluster      in spillInit(); (floatRa o intRa) cluster
# Line 218  Line 222 
222    
223   (* primitives for generation of DEC alpha instruction flowgraphs *)   (* primitives for generation of DEC alpha instruction flowgraphs *)
224    structure FlowGraphGen =    structure FlowGraphGen =
225       FlowGraphGen(structure Flowgraph = F       ClusterGen(structure Flowgraph = F
226                    structure InsnProps = P                    structure InsnProps = P
227                    structure MLTree = MLTree                    structure MLTree = MLTree
228                    structure Stream = Emitter.S
229                    val optimize = optimizerHook                    val optimize = optimizerHook
230                    val output = BBSched.bbsched o RegAllocation.ra)                    val output = BBSched.bbsched o RegAllocation.ra)
231    
# Line 228  Line 233 
233    structure MLTreeGen =    structure MLTreeGen =
234       MLRiscGen(structure MachineSpec=Alpha32Spec       MLRiscGen(structure MachineSpec=Alpha32Spec
235                 structure MLTreeComp=                 structure MLTreeComp=
236                    Alpha32(structure Flowgen=FlowGraphGen                    Alpha(structure AlphaInstr=Alpha32Instr
237                            structure Alpha32Instr=Alpha32Instr                          structure AlphaMLTree=Alpha32MLTree
238                            structure Alpha32MLTree=Alpha32MLTree                          structure Stream = Emitter.S
239                            structure PseudoInstrs=Alpha32PseudoInstrs)                          structure PseudoInstrs=Alpha32PseudoInstrs
240                 structure Cells=Alpha32Cells                          val mode32bit = true (* simulate 32 bit mode *)
241                            val useSU = alpha32x
242                            val multCost = ref 8 (* just guessing *)
243                            val useMultByConst = ref false (* just guessing *)
244                           )
245                   structure Flowgen=FlowGraphGen
246                   structure Cells=AlphaCells
247                 structure C=Alpha32CpsRegs                 structure C=Alpha32CpsRegs
248                 structure PseudoOp=Alpha32PseudoOps)                 structure PseudoOp=Alpha32PseudoOps)
249    
# Line 244  Line 255 
255    
256  (*  (*
257   * $Log: alpha32CG.sml,v $   * $Log: alpha32CG.sml,v $
  * Revision 1.8  1999/03/22 21:06:15  george  
  *  new GC API (take II)  
  *  
258   * Revision 1.7  1999/03/22 17:22:11  george   * Revision 1.7  1999/03/22 17:22:11  george
259   *   Changes to support new GC API   *   Changes to support new GC API
260   *   *

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