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[smlnj] Log of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml
[smlnj] / sml / trunk / src / compiler / CodeGen / alpha32 / alpha32CG.sml  
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Log of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml

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Revision 1033 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 24 05:45:18 2002 UTC (17 years, 9 months ago) by george
File length: 3698 byte(s)
Diff to previous 1009
   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

Revision 1009 - (view) (download) (annotate) - [select for diffs]
Modified Wed Jan 9 19:44:22 2002 UTC (17 years, 10 months ago) by george
File length: 4977 byte(s)
Diff to previous 1003
	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 11 months ago) by george
File length: 5077 byte(s)
Diff to previous 984
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

Revision 984 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 21 19:00:08 2001 UTC (18 years ago) by george
File length: 5041 byte(s)
Diff to previous 909
  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Revision 909 - (view) (download) (annotate) - [select for diffs]
Modified Fri Aug 24 17:48:53 2001 UTC (18 years, 3 months ago) by george
File length: 4906 byte(s)
Diff to previous 823
removed clusters from MLRISC

Revision 823 - (view) (download) (annotate) - [select for diffs]
Modified Tue May 8 21:25:15 2001 UTC (18 years, 6 months ago) by george
File length: 4840 byte(s)
Diff to previous 796
omit frame pointer optimization

Revision 796 - (view) (download) (annotate) - [select for diffs]
Modified Tue Mar 6 00:04:33 2001 UTC (18 years, 8 months ago) by leunga
File length: 4616 byte(s)
Diff to previous 773

   Support for alternative control-flow, exception handlers added.

Revision 773 - (view) (download) (annotate) - [select for diffs]
Modified Mon Jan 8 16:18:37 2001 UTC (18 years, 10 months ago) by blume
File length: 4466 byte(s)
Diff to previous 744
merging changes from private branch

Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (18 years, 11 months ago) by leunga
File length: 4343 byte(s)
Diff to previous 657

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 657 - (view) (download) (annotate) - [select for diffs]
Modified Fri Jun 9 05:20:54 2000 UTC (19 years, 5 months ago) by leunga
File length: 3222 byte(s)
Diff to previous 651

     None of these changes should affect SML/NJ.  See HISTORY file for details.
     CVS Tag=leunga-20000609-various

Revision 651 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 5 months ago) by monnier
File length: 3236 byte(s)
Diff to previous 583
bring revisions from the vendor branch to the trunk

Revision 583 - (view) (download) (annotate) - [select for diffs]
Modified Thu Mar 23 21:52:30 2000 UTC (19 years, 8 months ago) by leunga
File length: 3236 byte(s)
Diff to previous 555

1. X86 fixes/changes

   a.  The old code generated for SETcc was completely wrong.
       The Intel optimization guide is VERY misleading.

2. ALPHA fixes/changes

   a.  Added the instructions LDBU, LDWU, STB, STW as per Fermin's suggestion.
   b.  Added a new mode byteWordLoadStores to the functor parameter to Alpha()
   c.  Added reassociation code for address computation.

Revision 555 - (view) (download) (annotate) - [select for diffs]
Modified Fri Mar 3 16:10:30 2000 UTC (19 years, 8 months ago) by george
File length: 3188 byte(s)
Diff to previous 546
lal-20000303-new mltree -- take II

Revision 546 - (view) (download) (annotate) - [select for diffs]
Modified Thu Feb 24 14:04:51 2000 UTC (19 years, 8 months ago) by george
File length: 2984 byte(s)
Diff to previous 499
  Changes to MLTREE

Revision 499 - (view) (download) (annotate) - [select for diffs]
Modified Tue Dec 7 15:44:50 1999 UTC (19 years, 11 months ago) by monnier
File length: 2911 byte(s)
Copied from: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml revision 498
Diff to previous 498
This commit was generated by cvs2svn to compensate for changes in r498,
which included commits to RCS files with non-trunk default branches.

Revision 498 - (view) (download) (annotate) - [select for diffs]
Modified Tue Dec 7 15:44:50 1999 UTC (19 years, 11 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 2911 byte(s)
Diff to previous 475
version 110.25

Revision 475 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 10 22:59:58 1999 UTC (20 years ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 2909 byte(s)
Diff to previous 469
version 110.24

Revision 469 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 10 22:42:52 1999 UTC (20 years ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 2922 byte(s)
Diff to previous 429
version 110.23

Revision 429 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (20 years, 2 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 2960 byte(s)
Diff to previous 418
version 110.21

Revision 418 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 23:51:27 1999 UTC (20 years, 2 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 8388 byte(s)
Diff to previous 411
version 110.20

Revision 411 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (20 years, 2 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 8982 byte(s)
Diff to previous 247
version 110.19

Revision 247 - (view) (download) (annotate) - [select for diffs]
Added Sat Apr 17 18:47:13 1999 UTC (20 years, 7 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/compiler/CodeGen/alpha32/alpha32CG.sml
File length: 8562 byte(s)
version 110.16

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