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[smlnj] View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml
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View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 5077 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.
(*
 * Alpha32 specific backend
 *)
structure Alpha32CG = 
  MachineGen
  ( structure I          = Alpha32Instr
    structure MachSpec   = Alpha32Spec
    structure ClientPseudoOps = Alpha32ClientPseudoOps
    structure PseudoOps  = Alpha32PseudoOps
    structure Ext        = SMLNJMLTreeExt(* generic extension *)
    structure CpsRegs    = Alpha32CpsRegs
    structure InsnProps  = Alpha32Props
    structure Asm        = Alpha32AsmEmitter
    structure Shuffle    = Alpha32Shuffle
   
    structure CCalls     = DummyCCallsFn (Alpha32MLTree)
    structure OmitFramePtr = struct
      exception NotImplemented
      structure CFG=Alpha32CFG
      structure I=Alpha32Instr
      val vfp = CpsRegs.vfp
      fun omitframeptr _ = raise NotImplemented
    end
      

    structure MLTreeComp=
       Alpha(structure AlphaInstr = Alpha32Instr
             structure AlphaMLTree = Alpha32MLTree
             structure PseudoInstrs = Alpha32PseudoInstrs
             structure ExtensionComp = SMLNJMLTreeExtComp
               (structure I = Alpha32Instr
                structure T = Alpha32MLTree
		structure CFG = Alpha32CFG
		structure TS = Alpha32MLTreeStream
               )
             val mode32bit = true (* simulate 32 bit mode *)
             val multCost = ref 8 (* just guessing *)
             val useMultByConst = ref false (* just guessing *)
             val byteWordLoadStores = ref false
             val SMLNJfloatingPoint = true (* must be true for SML/NJ *)
            )

    structure Jumps =
       AlphaJumps(structure Instr=Alpha32Instr
                  structure Shuffle=Alpha32Shuffle
		  structure MLTreeEval=Alpha32MLTreeEval)

    structure BackPatch =
       BBSched2(structure CFG=Alpha32CFG
                structure Jumps = Jumps
		structure Placement = DefaultBlockPlacement(Alpha32CFG)
                structure Emitter = Alpha32MCEmitter)

    structure RA = 
       RISC_RA
         (structure I         = Alpha32Instr
          structure Flowgraph = Alpha32CFG
          structure InsnProps = InsnProps 
          structure Rewrite   = AlphaRewrite(Alpha32Instr)
          structure Asm       = Alpha32AsmEmitter
          structure SpillHeur = ChaitinSpillHeur
          structure Spill     = RASpill(structure InsnProps = InsnProps
                                        structure Asm = Alpha32AsmEmitter)

          val sp    = I.C.stackptrR
          val spill = CPSRegions.spill

          structure SpillTable = SpillTable(Alpha32Spec)

          val architecture = Alpha32Spec.architecture

          val beginRA = SpillTable.spillInit

          fun pure _ = false

          (* make copies *)
          structure Int = 
          struct
              val avail     = Alpha32CpsRegs.availR
              val dedicated = Alpha32CpsRegs.dedicatedR

              fun copy((rds as [_], rss as [_]), _) =
                  I.copy{dst=rds, src=rss, impl=ref NONE, tmp=NONE}
                | copy((rds, rss), I.INSTR(I.COPY{tmp, ...})) =
                  I.copy{dst=rds, src=rss, impl=ref NONE, tmp=tmp}

              (* spill copy temp *)
              fun spillCopyTmp(an, I.INSTR(I.COPY{tmp,dst,src,impl}),loc) =
                  I.copy{tmp=SOME(I.Displace{base=sp, 
                                             disp=SpillTable.getRegLoc loc}),
                         dst=dst,src=src,impl=impl}

              (* spill register *)
              fun spillInstr{src,spilledCell,spillLoc,an} =
                  [I.store{stOp=I.STL, b=sp,
                           d=I.IMMop(SpillTable.getRegLoc spillLoc), 
                           r=src, mem=spill}]

              (* reload register *)
              fun reloadInstr{dst,spilledCell,spillLoc,an} =
                  [I.load{ldOp=I.LDL, b=sp, 
                          d=I.IMMop(SpillTable.getRegLoc spillLoc),
                          r=dst, mem=spill}]

              val mode = RACore.NO_OPTIMIZATION
          end
 
          structure Float =   
          struct
              val avail     = Alpha32CpsRegs.availF
              val dedicated = Alpha32CpsRegs.dedicatedF

              fun copy((fds as [_], fss as [_]), _) =
                  I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=NONE}
                | copy((fds, fss), I.INSTR(I.FCOPY{tmp, ...})) =
                  I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=tmp}

              fun spillCopyTmp(an, I.INSTR(I.FCOPY{tmp,dst,src,impl}),loc) =
                  I.fcopy{tmp=SOME(I.Displace{base=sp, 
                                          disp=SpillTable.getFregLoc loc}),
                          dst=dst,src=src,impl=impl}

              fun spillInstr(_, r,loc) =
                  [I.fstore{stOp=I.STT, b=sp, 
                            d=I.IMMop(SpillTable.getFregLoc loc), 
                            r=r, mem=spill}]

              fun reloadInstr(_, r,loc) =
                  [I.fload{ldOp=I.LDT, b=sp,
                           d=I.IMMop(SpillTable.getFregLoc loc), 
                           r=r, mem=spill}]

              val mode = RACore.NO_OPTIMIZATION
          end
         )
  )

root@smlnj-gforge.cs.uchicago.edu
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