Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml
ViewVC logotype

View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32CG.sml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 583 - (download) (annotate)
Thu Mar 23 21:52:30 2000 UTC (19 years, 5 months ago) by leunga
File size: 3236 byte(s)

1. X86 fixes/changes

   a.  The old code generated for SETcc was completely wrong.
       The Intel optimization guide is VERY misleading.

2. ALPHA fixes/changes

   a.  Added the instructions LDBU, LDWU, STB, STW as per Fermin's suggestion.
   b.  Added a new mode byteWordLoadStores to the functor parameter to Alpha()
   c.  Added reassociation code for address computation.
(*
 * Alpha32 specific backend
 *)
structure Alpha32CG = 
  MachineGen
  ( structure I          = Alpha32Instr
    structure MachSpec   = Alpha32Spec
    structure PseudoOps  = Alpha32PseudoOps
    structure CpsRegs    = Alpha32CpsRegs
    structure InsnProps  = Alpha32Props
    structure Asm        = Alpha32AsmEmitter
    structure Shuffle    = Alpha32Shuffle

    structure MLTreeComp=
       Alpha(structure AlphaInstr = Alpha32Instr
             structure AlphaMLTree = Alpha32MLTree
             structure PseudoInstrs = Alpha32PseudoInstrs
             structure ExtensionComp = SMLNJMLTreeExtComp
               (structure I = Alpha32Instr
                structure T = Alpha32MLTree
               )
             val mode32bit = true (* simulate 32 bit mode *)
             val multCost = ref 8 (* just guessing *)
             val useMultByConst = ref false (* just guessing *)
             val byteWordLoadStores = ref false
             val SMLNJfloatingPoint = true (* must be true for SML/NJ *)
            )

    structure Alpha32Jumps =
       AlphaJumps(structure Instr=Alpha32Instr
                  structure Shuffle=Alpha32Shuffle)

    structure BackPatch =
       BBSched2(structure Flowgraph = Alpha32FlowGraph
                structure Jumps = Alpha32Jumps
                structure Emitter = Alpha32MCEmitter)

    structure RA = 
       RegAlloc
         (structure I         = Alpha32Instr
          structure MachSpec  = Alpha32Spec
          structure Flowgraph = Alpha32FlowGraph
          structure CpsRegs   = Alpha32CpsRegs
          structure InsnProps = InsnProps 
          structure Rewrite   = AlphaRewrite(Alpha32Instr)
          structure Asm       = Alpha32AsmEmitter

          val sp = I.C.stackptrR
          val spill = CPSRegions.spill

          fun pure _ = false

          (* make copies *)
          fun copyR((rds as [_], rss as [_]), _) =
              I.COPY{dst=rds, src=rss, impl=ref NONE, tmp=NONE}
            | copyR((rds, rss), I.COPY{tmp, ...}) =
              I.COPY{dst=rds, src=rss, impl=ref NONE, tmp=tmp}
          fun copyF((fds as [_], fss as [_]), _) =
              I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=NONE}
            | copyF((fds, fss), I.FCOPY{tmp, ...}) =
              I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=tmp}

          (* spill copy temp *)
          fun spillCopyTmp(I.COPY{tmp,dst,src,impl},loc) =
              I.COPY{tmp=SOME(I.Displace{base=sp, disp=loc}),
                     dst=dst,src=src,impl=impl}
          fun spillFcopyTmp(I.FCOPY{tmp,dst,src,impl},loc) =
              I.FCOPY{tmp=SOME(I.Displace{base=sp, disp=loc}),
                      dst=dst,src=src,impl=impl}

          (* spill register *)
          fun spillInstrR(r,offset) =
              [I.STORE{stOp=I.STL, b=sp, d=I.IMMop offset, r=r, mem=spill}]
          fun spillInstrF(r,offset) =
              [I.FSTORE{stOp=I.STT, b=sp, d=I.IMMop offset, r=r, mem=spill}]

          (* reload register *)
          fun reloadInstrR(r,offset,rest) =
              I.LOAD{ldOp=I.LDL, b=sp, d=I.IMMop offset, r=r, mem=spill}::rest
          fun reloadInstrF(r,offset,rest) =
              I.FLOAD{ldOp=I.LDT, b=sp, d=I.IMMop offset, r=r, mem=spill}::rest
         )
  )

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0