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[smlnj] View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32PseudoInstrs.sml
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View of /sml/trunk/src/compiler/CodeGen/alpha32/alpha32PseudoInstrs.sml

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 2367 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.
functor Alpha32PseudoInstrs
  (Instr : ALPHAINSTR where Region=CPSRegions) : ALPHA_PSEUDO_INSTR = 
struct
  structure I = Instr
  structure T = I.T
  structure C = Instr.C
  structure CB = CellsBasis

  fun error msg = MLRiscErrorMsg.impossible("Alpha32PsuedoInstrs."^msg)

  type reduceOpnd = I.operand -> CB.cell

  val floatTmpOffset = I.IMMop 96	(* runtime system dependent *)
  val floatTmpOffset8 = I.IMMop(96+8)		(* " *)
  val divlOffset = I.IMMop 120			(* " *)
  val divluOffset = I.IMMop 124			(* " *)

  val stack = CPSRegions.stack
  val sp = C.stackptrR
  val zeroR = 31

  val makeCellset = List.foldl C.addReg C.empty 
  val defs = makeCellset (map C.GPReg [0, 23, 24, 25, 26, 28])
  val uses = makeCellset (map C.GPReg [16, 17])
  fun copyTmp() = SOME(I.Direct(C.newReg()))

  val r16 = C.GPReg 16
  val r17 = C.GPReg 17
  val r26 = C.GPReg 26
  val r27 = C.GPReg 27
  val r0  = C.GPReg 0

  fun divlv({ra, rb, rc}, reduceOpnd) = 
    [I.copy{dst=[r16, r17], src=[ra, reduceOpnd rb], impl=ref NONE, 
	    tmp=copyTmp()},
     I.load{ldOp=I.LDL, r=r27, b=sp, d=divlOffset, mem=stack},
     I.jsr{r=r26, b=r27, d=0, defs=defs, uses=uses, cutsTo=[], mem=stack},
     I.copy{dst=[rc], src=[r0], impl=ref NONE, tmp=NONE}]

  fun divlu({ra, rb, rc}, reduceOpnd) = 
    [I.copy{dst=[r16, r17], src=[ra, reduceOpnd rb], impl=ref NONE, 
	    tmp=copyTmp()},
     I.load{ldOp=I.LDL, r=r27, b=sp, d=divluOffset, mem=stack},
     I.jsr{r=r26, b=r27, d=0, defs=defs, uses=uses, cutsTo=[], mem=stack},
     I.copy{dst=[rc], src=[r0], impl=ref NONE, tmp=NONE}]

  fun unimplemented _ = error "unimplemented pseudo-instr"
  val divl  = unimplemented
  val divqv = unimplemented
  val divq  = unimplemented
  val divqu = unimplemented
  val remlv = unimplemented
  val reml  = unimplemented
  val remlu = unimplemented
  val remqv = unimplemented
  val remq  = unimplemented
  val remqu = unimplemented
     
  fun cvtlt({opnd, fd}, reduceOpnd) = 
  let val ra = reduceOpnd opnd
  in  [I.store{stOp=I.STQ, r=ra, b=sp, d=floatTmpOffset, mem=stack},
       I.fload{ldOp=I.LDT, r=fd, b=sp, d=floatTmpOffset, mem=stack},
       I.funary{oper=I.CVTQT, fb=fd, fc=fd}]
  end

  val cvtls = unimplemented
  val cvtqt = unimplemented
  val cvtqs = unimplemented
  val cvtsl = unimplemented
  val cvttl = unimplemented
  val cvtsq = unimplemented
  val cvttq = unimplemented
end

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