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[smlnj] View of /sml/trunk/src/compiler/CodeGen/hppa/hppaCG.sml
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View of /sml/trunk/src/compiler/CodeGen/hppa/hppaCG.sml

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 6080 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.
 * Hppa specific backend
structure HppaCG = 
  ( structure MachSpec   = HppaSpec
    structure ClientPseudoOps = HppaClientPseudoOps
    structure PseudoOps  = HppaPseudoOps
    structure Ext        = SMLNJMLTreeExt(* generic extension *)
    structure CpsRegs    = HppaCpsRegs
    structure InsnProps  = HppaProps
    structure Asm        = HppaAsmEmitter
    structure Shuffle    = HppaShuffle

    structure CCalls     = DummyCCallsFn (HppaMLTree)

    structure OmitFramePtr = struct
      exception NotImplemented
      structure CFG=HppaCFG
      structure I=HppaInstr
      val vfp = CpsRegs.vfp
      fun omitframeptr _ = raise NotImplemented

    structure HppaMillicode = HppaMillicode(HppaInstr)

    structure HppaLabelComp = HppaLabelComp(HppaInstr)

    structure MLTreeComp=
       Hppa(structure HppaInstr = HppaInstr
            structure HppaMLTree = HppaMLTree
            structure MilliCode=HppaMillicode
            structure LabelComp=HppaLabelComp
            structure ExtensionComp = SMLNJMLTreeExtComp
               (structure I = HppaInstr
                structure T = HppaMLTree
		structure CFG = HppaCFG
		structure TS = HppaMLTreeStream
            val costOfMultiply = ref 7
            val costOfDivision = ref 7

    structure Jumps =
       HppaJumps(structure Instr=HppaInstr
		 structure MLTreeEval=HppaMLTreeEval
                 structure Shuffle=HppaShuffle)

    structure BackPatch =
         (structure CFG = HppaCFG
	  structure Placement = DefaultBlockPlacement(HppaCFG)
          structure Jumps     = Jumps
          structure Emitter   = HppaMCEmitter
          structure DelaySlot = HppaDelaySlots
             (structure I=HppaInstr
              structure P=InsnProps)
          structure Props = InsnProps

    structure RA = 
         (structure I         = HppaInstr
          structure Flowgraph = HppaCFG
          structure InsnProps = InsnProps 
          structure Rewrite   = HppaRewrite(HppaInstr) 
          structure Asm       = HppaAsmEmitter
          structure SpillHeur = ChaitinSpillHeur
          structure Spill     = RASpill(structure InsnProps = InsnProps
                                        structure Asm = HppaAsmEmitter)

          (* NOTE: the spill offset grows backwards on the stack! 
          structure SpillTable = SpillTable(HppaSpec)

          val beginRA = SpillTable.spillInit

          val architecture = HppaSpec.architecture

          val sp        = I.C.stackptrR
          val spill     = CPSRegions.spill
          val tmpR      = I.C.asmTmpR
          val itow      = Word.fromInt
          val wtoi      = Word.toIntX
          fun low11(n)  = wtoi(Word.andb(itow n, 0wx7ff))
          fun high21(n) = wtoi(Word.~>>(itow n, 0w11))

          fun pure(I.INSTR(I.LOAD _)) = true
            | pure(I.INSTR(I.LOADI _)) = true
            | pure(I.INSTR(I.FLOAD _)) = true
            | pure(I.INSTR(I.FLOADX _)) = true
            | pure(I.INSTR(I.ARITH _)) = true
            | pure(I.INSTR(I.ARITHI _)) = true
            | pure(I.INSTR(I.FARITH _)) = true
            | pure(I.INSTR(I.FUNARY _)) = true
            | pure(I.INSTR(I.FCNV _)) = true
            | pure(I.ANNOTATION{i,...}) = pure i
            | pure _ = false
          (* make copy *) 
          structure Int =
             val avail = HppaCpsRegs.availR
             val dedicated = HppaCpsRegs.dedicatedR

             fun copy((rds as [_], rss as [_]), _) =
                 I.copy{dst=rds, src=rss, impl=ref NONE, tmp=NONE}
               | copy((rds, rss), I.INSTR(I.COPY{tmp, ...})) =
                 I.copy{dst=rds, src=rss, impl=ref NONE, tmp=tmp}

             (* spill copy temp *) 
             fun spillCopyTmp(_, I.INSTR(I.COPY{dst,src,tmp,impl}),loc) =
                 I.copy{dst=dst, src=src, impl=impl,
                                           disp= ~(SpillTable.getRegLoc loc)})}

             (* spill register *) 
             fun spillInstr{src,spilledCell,spillLoc,an} =
                 [I.store{st=I.STW, b=sp, 
                          d=I.IMMED(~(SpillTable.getRegLoc spillLoc)), 
                          r=src, mem=spill}]

             (* reload register *) 
             fun reloadInstr{dst,spilledCell,spillLoc,an} =
                          i=I.IMMED(~(SpillTable.getRegLoc spillLoc)), 
                          r=sp, t=dst, mem=spill}

             val mode = RACore.NO_OPTIMIZATION

          structure Float = 
             val avail = HppaCpsRegs.availF
             val dedicated = HppaCpsRegs.dedicatedF
             fun copy((fds as [_], fss as [_]), _) =
                 I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=NONE}
               | copy((fds, fss), I.INSTR(I.FCOPY{tmp, ...})) =
                 I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=tmp}
             fun spillCopyTmp(_,I.INSTR(I.FCOPY{dst,src,tmp,impl}),loc) =
                 I.fcopy{dst=dst, src=src, impl=impl,
                                        disp= ~(SpillTable.getFregLoc loc)})}
             fun spillInstr(_,r,loc) =
             let val offset = SpillTable.getFregLoc loc
             in  [I.ldil{i=I.IMMED(high21(~offset)), t=tmpR},
                  I.ldo{i=I.IMMED(low11(~offset)), b=tmpR, t=tmpR},
                  I.fstorex{fstx=I.FSTDX, b=sp, x=tmpR, r=r, mem=spill}
             fun reloadInstr(_,t,loc) =
             let val offset = SpillTable.getFregLoc loc
             in  [I.ldil{i=I.IMMED(high21(~offset)), t=tmpR}, 
                  I.ldo{i=I.IMMED(low11(~offset)), b=tmpR, t=tmpR},
                  I.floadx{flx=I.FLDDX, b=sp, x=tmpR, t=t, mem=spill} 

             val mode = RACore.NO_OPTIMIZATION

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