Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCG.sml
ViewVC logotype

View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCG.sml

Parent Directory Parent Directory | Revision Log Revision Log

Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 7 months ago) by george
File size: 4756 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.
 * PPC specific backend
structure PPCCG = 
  ( structure MachSpec   = PPCSpec
    structure ClientPseudoOps = PPCClientPseudoOps
    structure PseudoOps  = PPCPseudoOps
    structure Ext        = SMLNJMLTreeExt(* generic extension *)
    structure CpsRegs    = PPCCpsRegs
    structure InsnProps  = PPCProps
    structure Asm        = PPCAsmEmitter
    structure Shuffle    = PPCShuffle

    structure CCalls     = DummyCCallsFn (PPCMLTree)

    structure OmitFramePtr = struct
      exception NotImplemented
      structure CFG=PPCCFG
      structure I=PPCInstr
      val vfp = PPCCpsRegs.vfp
      fun omitframeptr _ = raise NotImplemented

    structure MLTreeComp=
       PPC(structure PPCInstr = PPCInstr
           structure PPCMLTree = PPCMLTree
           structure PseudoInstrs=
               PPCPseudoInstr(structure Instr=PPCInstr)
           structure ExtensionComp = SMLNJMLTreeExtComp
               (structure I = PPCInstr
                structure T = PPCMLTree
		structure CFG = PPCCFG
		structure TS = PPCMLTreeStream
           val bit64mode=false
           val multCost=ref 6 (* an estimate *)

    structure Jumps =
       PPCJumps(structure Instr=PPCInstr
		structure MLTreeEval=PPCMLTreeEval
                structure Shuffle=PPCShuffle)

    structure BackPatch =
       BBSched2(structure CFG = PPCCFG
		structure Placement = DefaultBlockPlacement(PPCCFG)
                structure Jumps = Jumps
                structure Emitter = PPCMCEmitter)

    structure RA = 
         (structure I         = PPCInstr
          structure Flowgraph = PPCCFG
          structure CpsRegs   = PPCCpsRegs
          structure InsnProps = InsnProps 
          structure Rewrite   = PPCRewrite(PPCInstr) 
          structure Asm       = PPCAsmEmitter
          structure SpillHeur = ChaitinSpillHeur
          structure Spill     = RASpill(structure InsnProps = InsnProps
                                        structure Asm = PPCAsmEmitter)

          structure SpillTable = SpillTable(PPCSpec)

          val architecture = PPCSpec.architecture

          val beginRA = SpillTable.spillInit

          val sp = I.C.stackptrR
          val spill = CPSRegions.spill

          fun pure _ = false

          structure Int = 
             val avail     = PPCCpsRegs.availR
             val dedicated = PPCCpsRegs.dedicatedR

             (* make copy *)
             fun copy((rds as [_], rss as [_]), _) =
                 I.copy{dst=rds, src=rss, impl=ref NONE, tmp=NONE}
               | copy((rds, rss), I.INSTR(I.COPY{tmp, ...})) =
                 I.copy{dst=rds, src=rss, impl=ref NONE, tmp=tmp}

             (* spill copy temp *)
             fun spillCopyTmp(_, I.INSTR(I.COPY{dst,src,tmp,impl}),loc) =
                 I.copy{dst=dst, src=src, impl=impl,
                                    disp=I.ImmedOp(SpillTable.getRegLoc loc)})}

              (* spill register *)
             fun spillInstr{src,spilledCell,spillLoc,an} =
                 [I.st{st=I.STW, ra=sp, 
                       d=I.ImmedOp(SpillTable.getRegLoc spillLoc),
                       rs=src, mem=spill}]
             (* reload register *)
             fun reloadInstr{dst,spilledCell,spillLoc,an} =
                 [I.l{ld=I.LWZ, ra=sp, 
                      d=I.ImmedOp(SpillTable.getRegLoc spillLoc), 
                      rt=dst, mem=spill}]

             val mode = RACore.NO_OPTIMIZATION
         structure Float =
             val avail     = PPCCpsRegs.availF
             val dedicated = PPCCpsRegs.dedicatedF

             fun copy((fds as [_], fss as [_]), _) =
                 I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=NONE}
               | copy((fds, fss), I.INSTR(I.FCOPY{tmp, ...})) =
                 I.fcopy{dst=fds, src=fss, impl=ref NONE, tmp=tmp}
             fun spillCopyTmp(_, I.INSTR(I.FCOPY{dst,src,tmp,impl}),loc) =
                 I.fcopy{dst=dst, src=src, impl=impl,
                                    disp=I.ImmedOp(SpillTable.getFregLoc loc)
             fun spillInstr(_, fs,loc) =
                 [I.stf{st=I.STFD, ra=sp, 
                        d=I.ImmedOp(SpillTable.getFregLoc loc), 
                        fs=fs, mem=spill}]
             fun reloadInstr(_, ft,loc) =
                 [I.lf{ld=I.LFD, ra=sp, d=I.ImmedOp(SpillTable.getFregLoc loc),
                       ft=ft, mem=spill}]

             val mode = RACore.NO_OPTIMIZATION

ViewVC Help
Powered by ViewVC 1.0.0