Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCpsRegs.sml
ViewVC logotype

View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCpsRegs.sml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 246 - (download) (annotate)
Sat Apr 17 18:47:12 1999 UTC (21 years, 3 months ago) by monnier
File size: 1078 byte(s)
This commit was generated by cvs2svn to compensate for changes in r245,
which included commits to RCS files with non-trunk default branches.
(* ppcCpsRegs.sml --- CPS registers used on the POWER PC
 *
 * COPYRIGHT (c) 1999  Bell Laboratories.
 *
 *)

structure PPCCpsRegs : CPSREGS = 
struct
  structure T = PPCMLTree
  structure SL = SortedList
  fun upto (from,to) = if from>to then [] else from::(upto (from+1,to))
  infix upto

  val exhaustedR = 0
  val exhausted	= SOME(T.CC 0)

  val allocptr 	= T.REG 14
  val limitptr 	= T.REG 15
  val storeptr	= T.REG 16
  val stdlink	= T.REG 17
  val stdclos	= T.REG 18
  val stdarg	= T.REG 19
  val stdcont  	= T.REG 20
  val exnptr	= T.REG 21
  val varptr	= T.REG 22
  val baseptr   = T.REG 23
  val stackptr	= T.REG 1
  val gcLink	= T.REG PPCCells.lr

  val miscregs =  map T.REG ([24,25,26,27,29,30,31] @ (3 upto 13))
  val calleesave = Array.fromList(miscregs)
  val floatregs = map T.FREG (1 upto 31)
  val savedfpregs = []

  val allRegs = SL.uniq(0 upto 31)

  val availR = 
    map (fn T.REG r => r)
         ([stdlink, stdclos, stdarg, stdcont] @ miscregs)
  val dedicatedR = SL.remove(SL.uniq availR, allRegs)

  val availF = 1 upto 31
  val dedicatedF = [0]
end

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0