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[smlnj] View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCpsRegs.sml
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View of /sml/trunk/src/compiler/CodeGen/ppc/ppcCpsRegs.sml

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Revision 744 - (download) (annotate)
Fri Dec 8 04:11:42 2000 UTC (19 years, 8 months ago) by leunga
File size: 1406 byte(s)

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack
(* ppcCpsRegs.sml --- CPS registers used on the POWER PC
 *
 * COPYRIGHT (c) 1999  Bell Laboratories.
 *
 *)

structure PPCCpsRegs : CPSREGS = 
struct
  structure T = PPCMLTree
  fun upto (from,to) = if from>to then [] else from::(upto (from+1,to))
  infix upto

  val GP = PPCCells.GPReg
  val FP = PPCCells.FPReg
  val CC = PPCCells.Reg PPCCells.CC

  fun REG r = T.REG(32, GP r) 
  fun FREG f = T.FREG(64, FP f)

  val exhaustedR = CC 0
  val exhausted	= SOME(T.CC(T.GTU,exhaustedR)) 

  val allocptr 	= REG(14) 
  val limitptr 	= REG(15)
  val storeptr	= REG(16)
  val stdlink	= REG(17)
  val stdclos	= REG(18)
  val stdarg	= REG(19)
  val stdcont  	= REG(20)
  val exnptr	= REG(21)
  val varptr	= REG(22)
  val baseptr   = REG(23)
  val stackptr	= REG(1)
  val gcLink	= T.REG(32,PPCCells.lr) 

  val miscregs =  map REG ([24,25,26,27,29,30,31] @ (3 upto 13)) 
  val calleesave = Array.fromList(miscregs)
  val floatregs = map FREG (1 upto 31)
  val savedfpregs = []

  val availR = 
    map (fn T.REG(_,r) => r)
         ([stdlink, stdclos, stdarg, stdcont] @ miscregs)

  local
      structure SC = PPCCells.SortedCells
      val -- = SC.difference
      infix --
  in
      val allRegs = map GP (0 upto 31)
      val dedicatedR = SC.return (SC.uniq allRegs -- SC.uniq availR)
  end

  val availF = map FP (1 upto 31)
  val dedicatedF = [FP 0]

  val signedGCTest = false
  val addressWidth = 32
end

root@smlnj-gforge.cs.uchicago.edu
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