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[smlnj] Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcCpsRegs.sml
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Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcCpsRegs.sml

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revision 410, Fri Sep 3 00:25:03 1999 UTC revision 411, Fri Sep 3 00:25:03 1999 UTC
# Line 8  Line 8 
8  struct  struct
9    structure T = SparcMLTree    structure T = SparcMLTree
10    structure SL = SortedList    structure SL = SortedList
11      structure C = SparcCells
12    
13    val stdarg    = T.REG 24  (* %i0 *)    val GP = C.GPReg
14    val stdcont   = T.REG 25  (* %i1 *)    val FP = C.FPReg
15    val stdclos   = T.REG 26  (* %i2 *)  
16    val stdlink   = T.REG 1   (* %g1 *)    val stdarg    = T.REG(32,GP 24)  (* %i0 *)
17    val baseptr   = T.REG 27  (* %i3 *)    val stdcont   = T.REG(32,GP 25)  (* %i1 *)
18      val stdclos   = T.REG(32,GP 26)  (* %i2 *)
19    val limitptr  = T.REG 4   (* %g4 *)    val stdlink   = T.REG(32,GP 1)   (* %g1 *)
20    val varptr    = T.REG 29  (* %i5 *)    val baseptr   = T.REG(32,GP 27)  (* %i3 *)
21    val exhausted = SOME(T.CC 65)   (* %psr *)  
22    val storeptr  = T.REG 5   (* %g5 *)    val limitptr  = T.REG(32,GP 4)   (* %g4 *)
23    val allocptr  = T.REG 6   (* %g6 *)    val varptr    = T.REG(32,GP 29)  (* %i5 *)
24    val exnptr    = T.REG 7   (* %g7 *)    val exhausted = SOME(T.CC(C.psr))   (* %psr *)
25      val storeptr  = T.REG(32,GP 5)   (* %g5 *)
26    val returnPtr = 15    val allocptr  = T.REG(32,GP 6)   (* %g6 *)
27    val gcLink    = T.REG returnPtr    val exnptr    = T.REG(32,GP 7)   (* %g7 *)
28    val stackptr  = T.REG 14  
29      val returnPtr = GP 15
30      val gcLink    = T.REG(32,returnPtr)
31      val stackptr  = T.REG(32,GP 14)
32    
33     (* Warning %o2 is used as the asmTmp     (* Warning %o2 is used as the asmTmp
34      *)      *)
35    val miscregs =    val miscregs =
36      map T.REG [2, 3,                            (* %g2-%g3 *)      map (fn r => T.REG(32,GP r))
37                  [2, 3,                            (* %g2-%g3 *)
38                 8, 9,                            (* %o0-%o1 *)                 8, 9,                            (* %o0-%o1 *)
39                 16, 17, 18, 19, 20, 21, 22, 23,  (* %l0-%l7 *)                 16, 17, 18, 19, 20, 21, 22, 23,  (* %l0-%l7 *)
40                 28, 31,                          (* %i4, %i6, %i7 *)                 28, 31,                          (* %i4, %i6, %i7 *)
# Line 38  Line 43 
43    
44    (* Note: We need at least one register for shuffling purposes. *)    (* Note: We need at least one register for shuffling purposes. *)
45    fun fromto(n, m, inc) = if n>m then [] else n :: fromto(n+inc, m, inc)    fun fromto(n, m, inc) = if n>m then [] else n :: fromto(n+inc, m, inc)
46    val floatregs = map T.FREG (fromto(0,31,2))    val floatregs = map (fn f => T.FREG(64,f)) (fromto(FP 0,FP 31,2))
47    val savedfpregs = []    val savedfpregs = []
48    
49    val allRegs = SL.uniq(fromto(0,31,1))    val allRegs = SL.uniq(fromto(GP 0,GP 31,1))
50    
51    val availR =    val availR =
52      map (fn T.REG r => r)      map (fn T.REG(_,r) => r)
53          ([stdlink, stdclos, stdarg, stdcont, gcLink] @ miscregs)          ([stdlink, stdclos, stdarg, stdcont, gcLink] @ miscregs)
54    val dedicatedR = SL.remove(SL.uniq availR, allRegs)    val dedicatedR = SL.remove(SL.uniq availR, allRegs)
55    
56    val availF = SL.uniq(fromto(0, 30, 2))    val availF = SL.uniq(fromto(FP 0, FP 30, 2))
57    val dedicatedF = []    val dedicatedF = []
58      val signedGCTest = false
59  end  end
60    
61  (*  (*

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