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[smlnj] Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcCpsRegs.sml
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Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcCpsRegs.sml

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revision 545, Thu Feb 24 13:56:44 2000 UTC revision 546, Thu Feb 24 14:04:51 2000 UTC
# Line 10  Line 10 
10    structure SL = SortedList    structure SL = SortedList
11    structure C = SparcCells    structure C = SparcCells
12    
13      type rexp = (unit, unit, unit, unit) T.rexp
14      type fexp = (unit, unit, unit, unit) T.fexp
15      type ccexp = (unit, unit, unit, unit) T.ccexp
16    
17    val GP = C.GPReg    val GP = C.GPReg
18    val FP = C.FPReg    val FP = C.FPReg
19    
20    val stdarg    = T.REG(32,GP 24)  (* %i0 *)    fun REG r = T.REG(32,GP r) : rexp
21    val stdcont   = T.REG(32,GP 25)  (* %i1 *)    fun FREG f = T.FREG(64,FP f) : fexp
22    val stdclos   = T.REG(32,GP 26)  (* %i2 *)  
23    val stdlink   = T.REG(32,GP 1)   (* %g1 *)    val stdarg    = REG(24) (* %i0 *)
24    val baseptr   = T.REG(32,GP 27)  (* %i3 *)    val stdcont   = REG(25) (* %i1 *)
25      val stdclos   = REG(26) (* %i2 *)
26    val limitptr  = T.REG(32,GP 4)   (* %g4 *)    val stdlink   = REG(1)  (* %g1 *)
27    val varptr    = T.REG(32,GP 29)  (* %i5 *)    val baseptr   = REG(27) (* %i3 *)
28    val exhausted = SOME(T.CC(C.psr))   (* %psr *)  
29    val storeptr  = T.REG(32,GP 5)   (* %g5 *)    val limitptr  = REG(4)  (* %g4 *)
30    val allocptr  = T.REG(32,GP 6)   (* %g6 *)    val varptr    = REG(29) (* %i5 *)
31    val exnptr    = T.REG(32,GP 7)   (* %g7 *)    val exhausted = SOME(T.CC(T.GTU,C.psr))  (* %psr *)
32      val storeptr  = REG(5)  (* %g5 *)
33      val allocptr  = REG(6)  (* %g6 *)
34      val exnptr    = REG(7)  (* %g7 *)
35    
36    val returnPtr = GP 15    val returnPtr = GP 15
37    val gcLink    = T.REG(32,returnPtr)    val gcLink    = T.REG(32,returnPtr) : rexp
38    val stackptr  = T.REG(32,GP 14)    val stackptr  = REG(14)
39    
40     (* Warning %o2 is used as the asmTmp     (* Warning %o2 is used as the asmTmp
41      *)      *)
42    val miscregs =    val miscregs =
43      map (fn r => T.REG(32,GP r))      map REG
44                [2, 3,                            (* %g2-%g3 *)                [2, 3,                            (* %g2-%g3 *)
45                 8, 9,                            (* %o0-%o1 *)                 8, 9,                            (* %o0-%o1 *)
46                 16, 17, 18, 19, 20, 21, 22, 23,  (* %l0-%l7 *)                 16, 17, 18, 19, 20, 21, 22, 23,  (* %l0-%l7 *)
# Line 43  Line 50 
50    
51    (* Note: We need at least one register for shuffling purposes. *)    (* Note: We need at least one register for shuffling purposes. *)
52    fun fromto(n, m, inc) = if n>m then [] else n :: fromto(n+inc, m, inc)    fun fromto(n, m, inc) = if n>m then [] else n :: fromto(n+inc, m, inc)
53    val floatregs = map (fn f => T.FREG(64,f)) (fromto(FP 0,FP 31,2))    val floatregs = map FREG (fromto(0,31,2))
54    val savedfpregs = []    val savedfpregs = []
55    
56    val allRegs = SL.uniq(fromto(GP 0,GP 31,1))    val allRegs = SL.uniq(fromto(GP 0,GP 31,1))

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