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[smlnj] Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcPseudoInstrs.sml
 [smlnj] / sml / trunk / src / compiler / CodeGen / sparc / sparcPseudoInstrs.sml

# Diff of /sml/trunk/src/compiler/CodeGen/sparc/sparcPseudoInstrs.sml

revision 1182, Thu Mar 28 16:41:29 2002 UTC revision 1183, Fri Mar 29 19:09:48 2002 UTC
# Line 35  Line 35
35    val TVS = I.ticc{t=I.BVS,cc=I.ICC,r=C.r0,i=I.IMMED 7}    val TVS = I.ticc{t=I.BVS,cc=I.ICC,r=C.r0,i=I.IMMED 7}
36
37        (* overflows iff Y != (d ~>> 31) *)        (* overflows iff Y != (d ~>> 31) *)
38    fun smul_native({r, i, d}, reduceOpnd) =    fun smult_native({r, i, d}, reduceOpnd) =
39        let val t1 = C.newReg()        let val t1 = C.newReg()
40            val t2 = C.newReg()            val t2 = C.newReg()
41        in  [I.arith{a=I.SMUL,r=r,i=i,d=d},        in  [I.arith{a=I.SMUL,r=r,i=i,d=d},
# Line 45  Line 45
45             TNE             TNE
46            ]            ]
47        end        end
48
49      fun smul_native({r, i, d}, reduceOpnd) =
50          [I.arith{a=I.SMUL,r=r,i=i,d=d}]
51
52    fun udiv_native({r,i,d},reduceOpnd) =    fun udiv_native({r,i,d},reduceOpnd) =
53        [I.wry{r=C.r0,i=I.REG C.r0},        [I.wry{r=C.r0,i=I.REG C.r0},
54         I.arith{a=I.UDIV,r=r,i=i,d=d}]         I.arith{a=I.UDIV,r=r,i=i,d=d}]
55
56     (* May overflow if MININT div -1 *)     (* May overflow if MININT div -1 *)
57    fun sdiv_native({r,i,d},reduceOpnd) =    fun sdivt_native({r,i,d},reduceOpnd) =
58        let val t1 = C.newReg()        let val t1 = C.newReg()
59        in  [I.shift{s=I.SRA,r=r,i=I.IMMED 31,d=t1},        in  [I.shift{s=I.SRA,r=r,i=I.IMMED 31,d=t1},
60             I.wry{r=t1,i=I.REG C.r0},             I.wry{r=t1,i=I.REG C.r0},
# Line 59  Line 63
63            ]            ]
64        end        end
65
66      fun sdiv_native({r,i,d},reduceOpnd) =
67          let val t1 = C.newReg()
68          in  [I.shift{s=I.SRA,r=r,i=I.IMMED 31,d=t1},
69               I.wry{r=t1,i=I.REG C.r0},
70               I.arith{a=I.SDIV,r=r,i=i,d=d}
71              ]
72          end
73
74    (*    (*
75     * Registers %o2, %o3 are used to pass arguments to ml_mul and ml_div     * Registers %o2, %o3 are used to pass arguments to ml_mul and ml_div
76     * Result is returned in %o2.     * Result is returned in %o2.
# Line 96  Line 108
108
109       (* Generate native versions of the instructions *)       (* Generate native versions of the instructions *)
110    val umul32 = if native then umul_native else umul    val umul32 = if native then umul_native else umul
111    fun smul32 _ = error "smul32"    val smul32 : format1 =
112    val smul32trap = if native then smul_native else smultrap        if native then smul_native else (fn _ => error "smul32")
113      val smul32trap = if native then smult_native else smultrap
114    val udiv32 = if native then udiv_native else udiv    val udiv32 = if native then udiv_native else udiv
115    fun sdiv32 _ = error "sdiv32"    val sdiv32 : format1 =
116    val sdiv32trap = if native then sdiv_native else sdivtrap        if native then sdiv_native else (fn _ => error "sdiv32")
117      val sdiv32trap = if native then sdivt_native else sdivtrap
118
119    val overflowtrap32 = (* tvs 0x7 *)    val overflowtrap32 = (* tvs 0x7 *)
120                         [I.ticc{t=I.BVS,cc=I.ICC,r=C.r0,i=I.IMMED 7}]                         [I.ticc{t=I.BVS,cc=I.ICC,r=C.r0,i=I.IMMED 7}]

Legend:
 Removed from v.1182 changed lines Added in v.1183