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[smlnj] Diff of /sml/trunk/src/compiler/CodeGen/x86/x86CpsRegs.sml
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Diff of /sml/trunk/src/compiler/CodeGen/x86/x86CpsRegs.sml

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revision 430, Wed Sep 8 09:47:00 1999 UTC revision 546, Thu Feb 24 14:04:51 2000 UTC
# Line 11  Line 11 
11    structure T = X86MLTree    structure T = X86MLTree
12    structure C = X86Cells    structure C = X86Cells
13    
14      type rexp = (unit, unit, unit, unit) T.rexp
15      type fexp = (unit, unit, unit, unit) T.fexp
16      type ccexp = (unit, unit, unit, unit) T.ccexp
17    
18    fun upto(from, to) = if from>to then [] else from::(upto (from+1,to))    fun upto(from, to) = if from>to then [] else from::(upto (from+1,to))
19    infix upto    infix upto
20    
# Line 22  Line 26 
26    val edx = T.REG(32, C.edx)    val esi = T.REG(32, C.esi)    val edx = T.REG(32, C.edx)    val esi = T.REG(32, C.esi)
27    val ebx = T.REG(32, C.ebx)    val edi = T.REG(32, C.edi)    val ebx = T.REG(32, C.ebx)    val edi = T.REG(32, C.edi)
28    
29    fun regInMem i = T.LOAD(32, T.ADD(32, esp, T.LI i), CPSRegions.memory)    fun regInMem i =
30          T.LOAD(32, T.ADD(32, esp, T.LI i), CPSRegions.memory) : rexp
31    
32    val allocptr  = edi    val allocptr  = edi
33    val stdarg    = ebp    val stdarg    = ebp
# Line 36  Line 41 
41    val storeptr  = regInMem 24    val storeptr  = regInMem 24
42    val varptr    = regInMem 28    val varptr    = regInMem 28
43    
44    val stdlink   = T.REG(32, GP 8)               (* vreg 0 *)    val stdlink   = T.REG(32, GP 8) : rexp                (* vreg 0 *)
45    val stdclos   = T.REG(32, GP 9)               (* vreg 1 *)    val stdclos   = T.REG(32, GP 9) : rexp                (* vreg 1 *)
46    
47    fun mkVregList(n, 0) = []    fun mkVregList(n, 0) = []
48      | mkVregList(n, cnt) = T.REG(32, GP n)::mkVregList(n+1, cnt-1)      | mkVregList(n, cnt) = T.REG(32, GP n)::mkVregList(n+1, cnt-1)
49    
50    (* miscregs = {ebx,ecx,edx,r10,r11,...r31} *)    (* miscregs = {ebx,ecx,edx,r10,r11,...r31} *)
51    val miscregs  = ebx::ecx::edx::mkVregList(10, X86Runtime.numVregs - 2)    val miscregs : rexp list =
52          ebx::ecx::edx::mkVregList(10, X86Runtime.numVregs - 2)
53    
54    val calleesave = Array.fromList miscregs    val calleesave = Array.fromList miscregs
55    val exhausted = NONE    val exhausted = NONE
56    
57    val floatregs = map (fn f => T.FREG(64,f)) ((FP 8) upto (FP 31))    val floatregs : fexp list =
58          map (fn f => T.FREG(64,f)) ((FP 8) upto (FP 31))
59    val savedfpregs = []    val savedfpregs = []
60    
61    val availR = map (fn T.REG(_,r) => r) [ebp, esi, ebx, ecx, edx, eax]    val availR = map (fn T.REG(_,r) => r) [ebp, esi, ebx, ecx, edx, eax]

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Removed from v.430  
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  Added in v.546

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