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[smlnj] Diff of /MLRISC/trunk/amd64/instructions/amd64Instr.sml
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Diff of /MLRISC/trunk/amd64/instructions/amd64Instr.sml

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revision 2804, Mon Oct 22 04:20:02 2007 UTC revision 2805, Mon Oct 22 07:33:14 2007 UTC
# Line 239  Line 239 
239     | BINARY of {binOp:binaryOp, src:operand, dst:operand}     | BINARY of {binOp:binaryOp, src:operand, dst:operand}
240     | SHIFT of {shiftOp:shiftOp, src:operand, dst:operand, count:operand}     | SHIFT of {shiftOp:shiftOp, src:operand, dst:operand, count:operand}
241     | CMPXCHG of {lock:bool, sz:isize, src:operand, dst:operand}     | CMPXCHG of {lock:bool, sz:isize, src:operand, dst:operand}
242       | XADD of {lock:bool, sz:isize, src:operand, dst:operand}
243     | MULTDIV of {multDivOp:multDivOp, src:operand}     | MULTDIV of {multDivOp:multDivOp, src:operand}
244     | MUL3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}     | MUL3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}
245     | MULQ3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}     | MULQ3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}
# Line 299  Line 300 
300     val binary : {binOp:binaryOp, src:operand, dst:operand} -> instruction     val binary : {binOp:binaryOp, src:operand, dst:operand} -> instruction
301     val shift : {shiftOp:shiftOp, src:operand, dst:operand, count:operand} -> instruction     val shift : {shiftOp:shiftOp, src:operand, dst:operand, count:operand} -> instruction
302     val cmpxchg : {lock:bool, sz:isize, src:operand, dst:operand} -> instruction     val cmpxchg : {lock:bool, sz:isize, src:operand, dst:operand} -> instruction
303       val xadd : {lock:bool, sz:isize, src:operand, dst:operand} -> instruction
304     val multdiv : {multDivOp:multDivOp, src:operand} -> instruction     val multdiv : {multDivOp:multDivOp, src:operand} -> instruction
305     val mul3 : {dst:CellsBasis.cell, src2:Int32.int, src1:operand} -> instruction     val mul3 : {dst:CellsBasis.cell, src2:Int32.int, src1:operand} -> instruction
306     val mulq3 : {dst:CellsBasis.cell, src2:Int32.int, src1:operand} -> instruction     val mulq3 : {dst:CellsBasis.cell, src2:Int32.int, src1:operand} -> instruction
# Line 559  Line 561 
561     | BINARY of {binOp:binaryOp, src:operand, dst:operand}     | BINARY of {binOp:binaryOp, src:operand, dst:operand}
562     | SHIFT of {shiftOp:shiftOp, src:operand, dst:operand, count:operand}     | SHIFT of {shiftOp:shiftOp, src:operand, dst:operand, count:operand}
563     | CMPXCHG of {lock:bool, sz:isize, src:operand, dst:operand}     | CMPXCHG of {lock:bool, sz:isize, src:operand, dst:operand}
564       | XADD of {lock:bool, sz:isize, src:operand, dst:operand}
565     | MULTDIV of {multDivOp:multDivOp, src:operand}     | MULTDIV of {multDivOp:multDivOp, src:operand}
566     | MUL3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}     | MUL3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}
567     | MULQ3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}     | MULQ3 of {dst:CellsBasis.cell, src2:Int32.int, src1:operand}
# Line 617  Line 620 
620     and binary = INSTR o BINARY     and binary = INSTR o BINARY
621     and shift = INSTR o SHIFT     and shift = INSTR o SHIFT
622     and cmpxchg = INSTR o CMPXCHG     and cmpxchg = INSTR o CMPXCHG
623       and xadd = INSTR o XADD
624     and multdiv = INSTR o MULTDIV     and multdiv = INSTR o MULTDIV
625     and mul3 = INSTR o MUL3     and mul3 = INSTR o MUL3
626     and mulq3 = INSTR o MULQ3     and mulq3 = INSTR o MULQ3

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