Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32.sml
[smlnj] / sml / branches / SMLNJ / src / MLRISC / alpha32 / alpha32.sml  
ViewVC logotype

Diff of /sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32.sml

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 122, Sat Jun 6 15:05:38 1998 UTC revision 123, Mon Sep 7 16:19:55 1998 UTC
# Line 175  Line 175 
175     * In either case we sign extend the 32-bit value. This is compatible     * In either case we sign extend the 32-bit value. This is compatible
176     * with LDL which sign extends a 32-bit valued memory location.     * with LDL which sign extends a 32-bit valued memory location.
177     *)     *)
178    fun loadImmed32 (n, base, rd) = let    fun loadImmed32(0w0, base, rd) =
179      val low = W32.andb(n, 0w65535)              (* unsigned low 16 bits *)         emit(I.OPERATE{oper=I.ADDL, ra=base, rb=zeroOp, rc=rd})
180      val high = W32.div(n, 0w65536)                      (* Sign-extend *)      | loadImmed32(n, base, rd) = let
181      val (lowsgn, highsgn) =          val low = W32.andb(n, 0w65535)  (* unsigned (0 .. 65535) *)
182        if W32.<=(low, 0w32767) then (low, high)          val high = W32.~>>(n, 0w16)     (* signed (~32768 .. 32768] *)
183        else (W32.-(low,0w65536), W32.+(high,0w1))          fun loadimmed(0, high) = emit(I.LDAH{r=rd, b=base, d=I.IMMop(high)})
184      val highsgn' = W32.andb(highsgn, 0w65535)            | loadimmed(low, high) =
185                 (emit(I.LDA{r=rd, b=base, d=I.IMMop(low)});
186                  emit(I.LDAH{r=rd, b=rd, d=I.IMMop(high)}))
187    in    in
188      emit(I.LDA{r=rd, b=base, d=I.IMMop(W32.toIntX lowsgn)});          if W32.<(low, 0w32768) then loadimmed(W32.toInt low, W32.toIntX high)
189      if (highsgn' = 0w0) then ()          else let (* low = (32768 .. 65535) *)
190      else if highsgn' < 0w32768 then             val lowsgn = W32.-(low, 0w65536) (* signed (~1 .. ~32768)  *)
191        emit(I.LDAH{r=rd, b=rd, d=I.IMMop(W32.toIntX highsgn)})             val highsgn = W32.+(high, 0w1)   (* (~32768 .. 32768) *)
192      else             val ilow = W32.toIntX lowsgn
193        emit(I.LDAH{r=rd, b=rd,             val ihigh = W32.toIntX highsgn
194                    d=I.IMMop(W32.toIntX (W32.-(highsgn, 0w65536)))})           in
195               if ihigh <> 32768 then loadimmed(ilow, ihigh)
196               else let
197                   val tmpR = C.newReg()
198                 in
199                   (* you gotta do what you gotta do! *)
200                   emit(I.LDA{r=rd, b=base, d=I.IMMop(ilow)});
201                   emit(I.OPERATE{oper=I.ADDL, ra=zeroR, rb=I.IMMop 1, rc=tmpR});
202                   emit(I.OPERATE{oper=I.SLL, ra=tmpR, rb=I.IMMop 31, rc=tmpR});
203                   emit(I.OPERATE{oper=I.ADDL, ra=tmpR, rb=I.REGop rd, rc=rd})
204                 end
205             end
206    end    end
   
207    
208    fun orderedFArith (exp1, exp2, T.LR) = (fregAction exp1, fregAction exp2)    fun orderedFArith (exp1, exp2, T.LR) = (fregAction exp1, fregAction exp2)
209      | orderedFArith (exp1, exp2, T.RL) = let      | orderedFArith (exp1, exp2, T.RL) = let
Legend:
Removed from v.122  
changed lines
  Added in v.123
root@smlnj-gforge.cs.uchicago.edu
 ViewVC Help
Powered by ViewVC 1.0.0  
Powered By FusionForge