Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32Props.sml
ViewVC logotype

Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32Props.sml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 17 - (view) (download)
Original Path: sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32Props.sml

1 : monnier 16 (* alpha32Props.sml
2 :     *
3 :     * COPYRIGHT (c) 1996 Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     functor Alpha32Props
8 :     (structure Alpha32Instr : ALPHA32INSTR
9 :     val exnptrR : int list) : INSN_PROPERTIES =
10 :     struct
11 :     structure I = Alpha32Instr
12 :     structure C = I.C
13 :     structure LE = LabelExp
14 :    
15 :     fun error msg = MLRiscErrorMsg.impossible ("alpha32Props."^msg)
16 :    
17 :     val zeroR = 31
18 :    
19 :     datatype kind = IK_JUMP | IK_NOP | IK_INSTR
20 :     datatype target = LABELLED of Label.label | FALLTHROUGH | ESCAPES
21 :    
22 :     fun instrKind(I.BRANCH _) = IK_JUMP
23 :     | instrKind(I.FBRANCH _) = IK_JUMP
24 :     | instrKind(I.JMPL _) = IK_JUMP
25 :     | instrKind _ = IK_INSTR
26 :    
27 :     fun branchTargets(I.BRANCH(I.BR, _, lab)) = [LABELLED lab]
28 :     | branchTargets(I.BRANCH(_, _, lab)) = [LABELLED lab, FALLTHROUGH]
29 :     | branchTargets(I.FBRANCH(_, _, lab)) = [LABELLED lab, FALLTHROUGH]
30 :     | branchTargets(I.JMPL(_,[])) = [ESCAPES]
31 :     | branchTargets(I.JMPL(_,labs)) = map LABELLED labs
32 :     | branchTargets _ = error "branchTargets"
33 :    
34 :     fun moveTmpR(I.COPY{tmp=SOME(I.Direct r), ...}) = SOME r
35 :     | moveTmpR(I.FCOPY{tmp=SOME(I.FDirect f), ...}) = SOME f
36 :     | moveTmpR _ = NONE
37 :    
38 :     fun moveDstSrc(I.COPY{dst, src, ...}) = (dst, src)
39 :     | moveDstSrc(I.FCOPY{dst, src, ...}) = (dst, src)
40 :     | moveDstSrc _ = error "moveDstSrc"
41 :    
42 :     fun moveInstr(I.COPY _) = true
43 :     | moveInstr(I.FCOPY _) = true
44 :    
45 :     (* Technically these are valid move instructions however they are
46 :     not emitted by the code generator when emitting a move.
47 :     I expect them to occur rarely so don't bother with them.
48 :     | moveInstr(I.FOPERATE{oper=I.CPYS, fa, fb, ...}) = fa = fb
49 :     | moveInstr(I.OPERATE{oper=I.BIS, rb=I.REGop 31, ...}) = true
50 :     | moveInstr(I.ADDL(_,I.IMMop 0,_)) = true
51 :     | moveInstr(I.BIS(31,_,_)) = true
52 :     | moveInstr(I.SUBL(_,I.IMMop 0, _)) = true
53 :     | moveInstr(I.ADDL(_,I.REGop 31,_)) = true
54 :     | moveInstr(I.SUBL(_,I.REGop 31,_)) = true
55 :     | moveInstr(I.LDA{d=I.IMMop 0, ...}) = true
56 :     | moveInstr(I.LDAH{d=I.IMMop 0, ...}) = true
57 :     *)
58 :     | moveInstr _ = false
59 :    
60 :     val nop =
61 :     fn () => I.OPERATE{oper=I.BIS, ra=zeroR, rb=I.REGop zeroR, rc=zeroR}
62 :    
63 :     (* Resource usage *)
64 :     fun defUseR instr =
65 :     let
66 :     fun Oper {oper, ra, rb=I.REGop rb, rc} = ([rc], [ra, rb])
67 :     | Oper {oper, ra, rb, rc} = ([rc], [ra])
68 :     fun FMem (freg, (rd, _)) = ([], [rd])
69 :     fun trap (def,use) =(def, exnptrR @ use)
70 :     in
71 :     case instr of
72 :     (* load/store instructions *)
73 :     I.LDA{r, b, ...} => ([r], [b])
74 :     | I.LDAH{r, b, ...} => ([r], [b])
75 :     | I.LOAD{r, b, ...} => ([r], [b])
76 :     | I.STORE{r, b, ...} => ([], [r,b])
77 :     | I.FLOAD{b, ...} => ([], [b])
78 :     | I.FSTORE{b, ...} => ([], [b])
79 :     (* branch instructions *)
80 :     | I.JMPL ({r, b, ...},_) => ([r], [b])
81 :     | I.JSR({r, b, ...}, def, use) => (r:: #1 def, b:: #1 use)
82 :     | I.BRANCH(I.BR, reg, _) => ([reg], [])
83 :     | I.BRANCH(_, reg, _) => ([], [reg])
84 :     (* operate *)
85 :     | I.OPERATE arg => Oper arg
86 :     | I.PSEUDOARITH {oper, ra, rb=I.REGop rb, rc, tmps} =>
87 :     (rc:: #1 tmps, [ra, rb])
88 :     | I.PSEUDOARITH {oper, ra, rb, rc, tmps} => (rc:: #1 tmps, [ra])
89 :     | I.OPERATEV arg => trap(Oper arg)
90 :     (* copy *)
91 :     | I.COPY{dst, src, tmp=SOME(I.Direct r), ...} => (r::dst, src)
92 :     | I.COPY{dst, src, ...} => (dst, src)
93 :     (* floating operate *)
94 :     | I.FOPERATEV _ => trap([], [])
95 :     | I.TRAPB => trap([],[])
96 :     (* macro *)
97 :     | I.CALL_PAL{def,use, ...} => (def, use)
98 :    
99 :     | _ => ([],[])
100 :     end
101 :    
102 :     (* Use of FP registers *)
103 :     fun defUseF instr =
104 :     case instr of
105 :     I.DEFFREG freg => ([freg], [])
106 :     | I.FBRANCH(_, freg, lab) => ([],[freg])
107 :     | I.FLOAD{r, ...} => ([r], [])
108 :     | I.FSTORE{r, ...} => ([], [r])
109 :     | I.FOPERATE{fa, fb, fc, ...} => ([fc], [fa, fb])
110 :     | I.PSEUDOARITH{tmps, ...} => (#2 tmps, [])
111 :     | I.FOPERATEV{oper=I.CVTTQ, fa, fb, fc} => ([fc], [fa, fb])
112 :     | I.FOPERATEV{fa, fb, fc, ...} => ([fc], [fa, fb, fc])
113 :     | I.FCOPY{dst, src, tmp=SOME(I.FDirect f), ...} => (f::dst, src)
114 :     | I.FCOPY{dst, src, ...} => (dst, src)
115 :     | I.JSR(_,def,use) => (#2 def,#2 use)
116 :     | _ => ([],[])
117 :    
118 :    
119 :     (* These numbers are true of the DECchip 21064-AA implementation. *)
120 :     (* Load class *)
121 :     fun latency(I.LOAD _) = 5
122 :     | latency(I.FLOAD _) = 5
123 :    
124 :     | latency(I.OPERATE{oper, ...}) =
125 :     (case oper
126 :     of I.SRA => 2
127 :     | I.SRL => 2
128 :     | I.SLL => 2
129 :     | I.INSBL => 2
130 :     | I.EXTBL => 2
131 :     | I.EXTQH => 2
132 :     | I.MSKBL => 2
133 :     | I.MSKLH => 2
134 :     | I.CMPULE => 3
135 :     | I.CMPULT => 3
136 :     | I.CMPEQ => 3
137 :     | I.CMPLE => 3
138 :     | I.CMPLT => 3
139 :     | I.MULL => 21
140 :     | _ => 1
141 :     (*esac*))
142 :     | latency (I.OPERATEV{oper=I.MULLV, ...}) = 21
143 :    
144 :     (* Floating point *)
145 :     | latency(I.FOPERATEV{oper=I.DIVT, ...}) = 63
146 :     | latency(I.FOPERATEV _) = 6
147 :     | latency(I.FOPERATE _) = 6
148 :    
149 :     | latency(I.CALL_PAL _) = 30
150 :    
151 :     | latency _ = 1
152 :     end
153 :    
154 :    
155 :    
156 :     (*
157 :     * $Log: alpha32Props.sml,v $
158 :     * Revision 1.3 1998/02/16 13:57:44 george
159 :     * A register allocated temp is now associated with parallel COPYs
160 :     * instead of a dedicated register. The temp is used to break cycles.
161 :     *
162 :     * Revision 1.2 1997/08/29 11:00:06 george
163 :     * Added code to handle the new LDS, CVTLQ, DIVL and DIVLU instructions.
164 :     *
165 :     # Revision 1.1.1.1 1997/04/19 18:14:22 george
166 :     # Version 109.27
167 :     #
168 :     *)

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0