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[smlnj] Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32RegAlloc.sml
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Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32RegAlloc.sml

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Original Path: sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32RegAlloc.sml

1 : monnier 16 (* alpha32RegAlloc.sml --- alpha integer and floating register allocator
2 :     *
3 :     * COPYRIGHT (c) 1996 AT&T Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     (* Integer and floating register allocators are a partial application
8 :     * of a curried functor.
9 :     *)
10 :    
11 :    
12 :    
13 :     functor Alpha32RegAlloc(structure P : INSN_PROPERTIES
14 :     structure F : FLOWGRAPH
15 :     structure I : INSTRUCTIONS where C = Alpha32Cells
16 :     structure Asm : EMITTER_NEW
17 :     sharing Asm.F = F
18 :     sharing P.I = F.I = Asm.I = I) :
19 :     sig
20 :     functor IntRa (structure RaUser : RA_USER_PARAMS
21 :     where type I.operand = I.operand
22 :     and type I.instruction = I.instruction
23 :     (* should be: where I = I -- bug 1205 *)) : sig
24 :     datatype mode = REGISTER_ALLOCATION | COPY_PROPAGATION
25 :     val ra : mode -> F.cluster -> F.cluster
26 :     end
27 :     functor FloatRa (structure RaUser : RA_USER_PARAMS
28 :     where type I.operand = I.operand
29 :     and type I.instruction = I.instruction
30 :     (* should be: where I = I *)) : sig
31 :     datatype mode = REGISTER_ALLOCATION | COPY_PROPAGATION
32 :     val ra : mode -> F.cluster -> F.cluster
33 :     end
34 :     end =
35 :     struct
36 : monnier 106 structure C = I.C
37 : monnier 16 (* liveness analysis for general purpose registers *)
38 :     structure RegLiveness =
39 :     Liveness(structure Flowgraph=F
40 :     structure Instruction=I
41 : monnier 106 val defUse = P.defUse C.GP
42 : monnier 16 fun regSet c = #1 (c:Alpha32Cells.cellset)
43 :     fun cellset((_,f),r) = (r,f))
44 :    
45 :    
46 :     (* integer register allocator *)
47 :     functor IntRa =
48 :     RegAllocator
49 :     (structure RaArch = struct
50 :    
51 :     structure InsnProps = P
52 :     structure AsmEmitter = Asm
53 :     structure I = I
54 :     structure Liveness=RegLiveness
55 : monnier 106 val defUse = P.defUse C.GP
56 : monnier 16 val firstPseudoR = 32
57 : monnier 106 val maxPseudoR = Alpha32Cells.maxCell
58 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.GP
59 : monnier 16 fun regSet c = #1 (c:Alpha32Cells.cellset)
60 :     end)
61 :    
62 :    
63 :    
64 :     (* liveness analysis for floating point registers *)
65 :     structure FregLiveness =
66 :     Liveness(structure Flowgraph=F
67 :     structure Instruction=I
68 : monnier 106 val defUse = P.defUse C.FP
69 : monnier 16 fun regSet c = #2 (c:Alpha32Cells.cellset)
70 :     fun cellset((r,_),f) = (r,f))
71 :    
72 :     (* floating register allocator *)
73 :     functor FloatRa =
74 :     RegAllocator
75 :     (structure RaArch = struct
76 :    
77 :     structure InsnProps = P
78 :     structure AsmEmitter = Asm
79 :     structure Liveness=FregLiveness
80 :     structure I = I
81 :    
82 : monnier 106 val defUse = P.defUse C.FP
83 : monnier 16 val firstPseudoR = 32
84 : monnier 106 val maxPseudoR = Alpha32Cells.maxCell
85 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.FP
86 : monnier 16 fun regSet c = #2 (c:Alpha32Cells.cellset)
87 :     end)
88 :     end
89 :    
90 :    
91 :    
92 :    
93 :     (*
94 :     * $Log: alpha32RegAlloc.sml,v $
95 : monnier 106 * Revision 1.2 1998/05/19 15:43:26 george
96 :     * The instructions properties now exports a generic defUse function that is
97 :     * curried over the cellclass, i.e., defUseR and defUseF are gone.
98 :     *
99 : monnier 93 * Revision 1.1.1.1 1998/04/08 18:39:01 george
100 :     * Version 110.5
101 : monnier 16 *
102 :     *)

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