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Revision 1052 - (view) (download) (annotate) - [select for diffs]
Modified Wed Feb 6 04:04:48 2002 UTC (20 years, 5 months ago) by george
File length: 82902 byte(s)
Diff to previous 1033

  A bug fix from Allen.

  A typo causes extra fstp %st(0)'s to be generated at compensation
edges, which might cause stack underflow traps at runtime.  This
occurs in fft where there are extraneous fstps right before the 'into'
trap instruction (in this case they are harmless since none of the
integers overflow.)

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Revision 1033 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 24 05:45:18 2002 UTC (20 years, 5 months ago) by george
File length: 82902 byte(s)
Diff to previous 1025

   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

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Revision 1025 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 17 20:31:51 2002 UTC (20 years, 5 months ago) by leunga
File length: 82858 byte(s)
Diff to previous 1024

     Fixed a problem with the handling of CALLs in x86's "fast fp" mode.

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Revision 1024 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 17 19:30:59 2002 UTC (20 years, 5 months ago) by jhr
File length: 82405 byte(s)
Diff to previous 1009

  Added Allen's fix for the FP register allocator.

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Revision 1009 - (view) (download) (annotate) - [select for diffs]
Modified Wed Jan 9 19:44:22 2002 UTC (20 years, 5 months ago) by george
File length: 82404 byte(s)
Diff to previous 1003

	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

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Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (20 years, 7 months ago) by george
File length: 82366 byte(s)
Diff to previous 984

Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

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Revision 984 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 21 19:00:08 2001 UTC (20 years, 7 months ago) by george
File length: 82313 byte(s)
Diff to previous 925

  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

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Revision 925 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 14 15:26:29 2001 UTC (20 years, 9 months ago) by jhr
File length: 82469 byte(s)
Diff to previous 909

Added Allen's x86-fp.sml fix

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Revision 909 - (view) (download) (annotate) - [select for diffs]
Modified Fri Aug 24 17:48:53 2001 UTC (20 years, 10 months ago) by george
File length: 80906 byte(s)
Diff to previous 900

removed clusters from MLRISC

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Revision 900 - (view) (download) (annotate) - [select for diffs]
Modified Tue Aug 14 15:10:12 2001 UTC (20 years, 10 months ago) by jhr
File length: 80862 byte(s)
Diff to previous 895

  Moved CellSets from Cells to CellsBasis.

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Revision 895 - (view) (download) (annotate) - [select for diffs]
Modified Tue Jul 31 14:09:21 2001 UTC (20 years, 11 months ago) by george
File length: 80851 byte(s)
Diff to previous 889

    There was a bug where call instructions would mysteriously
    vanish. The call instruction had to be one that returned
    a floating point value.

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Revision 889 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jul 19 20:35:20 2001 UTC (20 years, 11 months ago) by george
File length: 80809 byte(s)
Diff to previous 815

Substantial simplification in the CELLS interface

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Revision 815 - (view) (download) (annotate) - [select for diffs]
Modified Fri May 4 05:09:10 2001 UTC (21 years, 2 months ago) by leunga
File length: 80741 byte(s)
Diff to previous 775

    Moby related MLRISC changes

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Revision 775 - (view) (download) (annotate) - [select for diffs]
Modified Fri Jan 12 01:17:51 2001 UTC (21 years, 5 months ago) by leunga
File length: 80244 byte(s)
Diff to previous 744

    Merging the types labexp and mltree.
    tag leunga-20010111-labexp=mltree

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Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (21 years, 6 months ago) by leunga
File length: 80226 byte(s)
Diff to previous 733

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

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Revision 733 - (view) (download) (annotate) - [select for diffs]
Modified Fri Nov 17 05:13:45 2000 UTC (21 years, 7 months ago) by blume
File length: 80715 byte(s)
Diff to previous 731

merged the big housecleaning patch (see HISTORY!)

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Revision 731 - (view) (download) (annotate) - [select for diffs]
Added Fri Nov 10 22:57:45 2000 UTC (21 years, 7 months ago) by leunga
File length: 80524 byte(s)

A new x86 floating point code generator.  By default it is off.
See HISTORY for details.   CVS tag=leunga-20001110-new-x86-fp