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[smlnj] View of /sml/trunk/src/compiler/CodeGen/ppc/ppcPseudoInstr.sml
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View of /sml/trunk/src/compiler/CodeGen/ppc/ppcPseudoInstr.sml

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (19 years, 9 months ago) by george
File size: 994 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.
functor PPCPseudoInstr
  (structure Instr : PPCINSTR
     where Region = CPSRegions) : PPC_PSEUDO_INSTR = 
  structure I = Instr
  structure C = Instr.C

  val stack = CPSRegions.stack
  val cvti2dTmpOff = 16			(* runtime system dependent *)
  val cvti2dConstOff = 8		(*            ''             *)
  val sp = C.stackptrR

  (* Cute little trick -- go figure *)
  fun cvti2d{reg, fd} = let
    val tmpR = C.newReg()
    val tmpF = C.newFreg()
    map I.INSTR
      [I.ARITHI{oper=I.XORIS, rt=tmpR, ra=reg, im=I.ImmedOp 32768},
       I.ST{st=I.STW, rs=tmpR, ra=sp, d=I.ImmedOp(cvti2dTmpOff+4), mem=stack},
       I.ARITHI{oper=I.ADDIS, rt=tmpR, ra=C.r0, im=I.ImmedOp(0x4330)},
       I.ST{st=I.STW, rs=tmpR, ra=sp, d=I.ImmedOp(cvti2dTmpOff), mem=stack},
       I.LF{ld=I.LFD, ft=fd, ra=sp, d=I.ImmedOp(cvti2dTmpOff), mem=stack},
       I.LF{ld=I.LFD, ft=tmpF, ra=sp, d=I.ImmedOp(cvti2dConstOff), mem=stack},
       I.FARITH{oper=I.FSUB, ft=fd, fa=fd, fb=tmpF, Rc=false}]

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