Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Annotation of /sml/trunk/src/compiler/OldCGen/rs6000/rs6000instrset.sml
ViewVC logotype

Annotation of /sml/trunk/src/compiler/OldCGen/rs6000/rs6000instrset.sml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 16 - (view) (download)

1 : monnier 16 (* rs6000instrset.sml
2 :     *
3 :     * COPYRIGHT (c) 1996 Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     (** IBM RS6000 Instruction set *)
8 :     structure RS6000InstrSet = struct
9 :    
10 :     fun error msg = ErrorMsg.impossible ("RS6KInstrSet." ^ msg)
11 :    
12 :     datatype 'lab info = INFO of {addrOf: 'lab -> int, nameOf: 'lab -> string}
13 :     (**
14 :     abstype register = REGISTER of int
15 :     with
16 :     datatype register_rep = Reg' of int | Freg' of int
17 :     fun Reg i = REGISTER i
18 :     fun Freg i = REGISTER(i+32)
19 :     fun reg_rep (REGISTER i) = if i<32 then Reg' i
20 :     else Freg'(i-32)
21 :     fun reg_eq(REGISTER r,REGISTER s) = r=s
22 :     end
23 :     **)
24 :     datatype register = Reg of int | Freg of int
25 :     datatype specialReg = LR | MQ
26 :     datatype 'label EA = Direct of register
27 :     | Immed of int
28 :     | Immed32 of Word32.word
29 :     | ImmedLab of 'label
30 :    
31 :     datatype 'label signedlabel = POSLAB of 'label | NEGLAB of 'label
32 :     type 'label labexp = 'label signedlabel * int
33 :    
34 :     datatype 'label eaOpnd = Immed16Op of int
35 :     | RegOp of register
36 :     | LabelOp of 'label labexp
37 :     | HiLabOp of 'label labexp
38 :     | LoLabOp of 'label labexp
39 :    
40 :     datatype 'label branch24Off = Label24Off of 'label labexp
41 :    
42 :     datatype 'label branch16Off = Label16Off of 'label labexp
43 :    
44 :     datatype shamt = RegShift of register
45 :     | Int5Shift of int
46 :    
47 :     (* Note: the limitReg is hardwired into runtime/signal.c *)
48 :     val stackReg = Reg 1
49 :     val allocReg = Reg 14
50 :     val limitReg = Reg 15
51 :     val exnptrReg = Reg 21
52 :     val baseReg = Reg 23
53 :     val maskReg = Reg 29
54 :     val constBaseRegOffset = 32764
55 :     val fLoadStoreOff = 24 (* rely on RS6000.prim.asm *)
56 :    
57 :     datatype condition = LT | GT | EQ | SO (* cr0 *)
58 :     | FL | FG | FE | UN (* cr1 *)
59 :     | FX | FEX | VX | OX (* cr2 *)
60 :    
61 :     datatype 'label sdi =
62 :     SETBASEADDR of 'label * register
63 :     | LOADADDR of register * 'label * int
64 :     | LOAD of register * 'label * int
65 :     | LOADF of register * 'label * int * register
66 :     | BRANCH of condition * bool * 'label * register * 'label
67 :     | FBRANCH of condition * int * bool * 'label * register * 'label
68 :    
69 :     fun split n = let
70 :     val hi = Word.~>>(Word.fromInt n, 0w16)
71 :     val lo = Word.andb(Word.fromInt n, 0w65535)
72 :     in
73 :     if lo < 0w32768 then (hi,lo) else (hi+0w1, lo-0w65536)
74 :     end
75 :    
76 :     fun labelValue (INFO{addrOf,...}) (POSLAB lab,k) = k + addrOf lab
77 :     | labelValue (INFO{addrOf,...}) (NEGLAB lab,k) = k - addrOf lab
78 :    
79 :     fun hiLabelValue info labexp = #1 (split (labelValue info labexp))
80 :     fun loLabelValue info labexp = #2 (split (labelValue info labexp))
81 :    
82 :     local
83 :     fun labelVal(info,labexp) = let exception BranchOffset
84 :     val labOff = labelValue info labexp
85 :     in
86 :     labOff div 4
87 :     end
88 :     in
89 :     fun labBranch24Off info (Label24Off labexp) = labelVal(info,labexp)
90 :     fun labBranch16Off info (Label16Off labexp) = labelVal(info,labexp)
91 :     end
92 :    
93 :     datatype 'l instruction =
94 :     NOP
95 :    
96 :     | B of 'l branch24Off (* long branch *)
97 :     | BB of condition * bool * 'l branch16Off
98 :     | BBF of condition * int * bool * 'l branch16Off
99 :     | BR of unit (* branch via link reg *)
100 :    
101 :     | LBZ of register * register * 'l eaOpnd (* load byte and zero *)
102 :     | L of register * register * 'l eaOpnd (* load word *)
103 :     | LFD of register * register * 'l eaOpnd (* load float *)
104 :     | LIU of register * 'l eaOpnd (* load immediate upper *)
105 :    
106 :     | STB of register * register * 'l eaOpnd
107 :     | ST of register * register * 'l eaOpnd (* store word *)
108 :     | STFD of register * register * 'l eaOpnd (* store floating double *)
109 :    
110 :     | FMR of register * register (* floating move *)
111 :     | MTSPR of specialReg * register (* move to special reg *)
112 :     | CAL of register * register * 'l eaOpnd (* calculate address lower *)
113 :    
114 :     | A of register * register * 'l eaOpnd (* Add w/o overflow detection *)
115 :     | AO of register * register * register (* Add w overflow detection *)
116 :     | FAO of register * register * register (* floating add w overflow *)
117 :    
118 :     (** Subtract **)
119 :     | SF of register * register * 'l eaOpnd (* sub from w/o overflow *)
120 :     | SFO of register * register * register (* sub from w. overflow *)
121 :     | FSO of register * register * register (* float sub from w. overflow *)
122 :    
123 :     | MULS of register * register * register (* mult w/o overflow *)
124 :     | MULSO of register * register * register (* mult w overflow *)
125 :     | FMO of register * register * register (* floating mult w overflow *)
126 :    
127 :     | DIV of register * register * register (* div w/o overflow *)
128 :     | DIVS of register * register * register (* div w. overflow *)
129 :     | FDO of register * register * register (* floating div. w overflow *)
130 :    
131 :     | FNEG of register * register (* floating negate *)
132 :     | FABS of register * register (* floating absolute *)
133 :    
134 :     (* comparisons *)
135 :     | CMP of register * 'l eaOpnd (* compare signed *)
136 :     | CMPL of register * register (* compare logical (unsigned) *)
137 :     | FCMP of register * register (* floating compare *)
138 :     | CROR of condition * condition * condition (* cr bit field OR *)
139 :    
140 :     (* logical *)
141 :     | AND of register * register * 'l eaOpnd (* and *)
142 :     | OR of register * register * 'l eaOpnd (* or *)
143 :     | XOR of register * register * 'l eaOpnd (* xor *)
144 :     | XORU of register * register * 'l eaOpnd (* xor upper *)
145 :    
146 :     (* shift *)
147 :     | SL of register * register * shamt (* shift left *)
148 :     | SRA of register * register * shamt (* shift right *)
149 :     | SRL of register * register * shamt (* shift right logical *)
150 :    
151 :     | MTFSB1 of int (* set bit in FPSCR *)
152 :     | TRAP of unit (* trap always *)
153 :     end
154 :    
155 :    
156 :     (*
157 :     * $Log: rs6000instrset.sml,v $
158 :     * Revision 1.3 1997/11/14 21:48:10 jhr
159 :     * Restored the support for the Power architecture; the PowerPC code
160 :     * generator will be MLRisc based.
161 :     *
162 :     * Revision 1.2 1997/08/25 16:43:34 jhr
163 :     * Replaced some old Power architecture instructions with PowerPC instructions.
164 :     * This means that the Power architecture is no longer supported by this
165 :     * code generator. Also improved implementation of emitString.
166 :     *
167 :     * Revision 1.1.1.1 1997/01/14 01:38:45 george
168 :     * Version 109.24
169 :     *
170 :     *)

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0