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[smlnj] Annotation of /sml/trunk/src/compiler/OldCGen/rs6000/rs6000mc.sml
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Annotation of /sml/trunk/src/compiler/OldCGen/rs6000/rs6000mc.sml

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1 : monnier 16 (* rs6000mc.sml
2 :     *
3 :     * COPYRIGHT (c) 1996 Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     (** IBM RS6000 machine code generator **)
8 :     structure KeepRS6000MCode : sig
9 :     val code : Word8Array.array ref
10 :     val getCodeString : unit -> Word8Vector.vector
11 :     val cleanup : unit -> unit
12 :     end =
13 :     struct
14 :     open Word8Array
15 :     val code = ref (array(0,0w0))
16 :     fun getCodeString () = let
17 :     val s = extract (!code, 0, SOME(length (!code)))
18 :     in
19 :     code := array(0, 0w0); s
20 :     end
21 :     fun cleanup () = code := array(0,0w0)
22 :     end
23 :    
24 :     structure RS6000MCodeEmitter : EMITTER =
25 :     struct
26 :    
27 :     structure M = RS6000InstrSet
28 :     structure K = KeepRS6000MCode
29 :     open M
30 :    
31 :     fun error msg = ErrorMsg.impossible ("RS6000MCodeEmitter." ^ msg)
32 :    
33 :     val << = Word.<<
34 :     val >> = Word.>>
35 :     val ~>> = Word.~>>
36 :     val || = Word.orb
37 :     val & = Word.andb
38 :     infix << >> ~>> || &
39 :    
40 :     val itow = Word.fromInt
41 :    
42 :     val loc = ref 0
43 :    
44 :     fun init n = (K.code := Word8Array.array(n, 0w0); loc := 0)
45 :    
46 :     fun emitByte' b = let
47 :     val i = !loc
48 :     in
49 :     loc := i+1; Word8Array.update (!K.code, i, b)
50 :     end
51 :    
52 :     fun emitByte n = emitByte'(Word8.fromLargeWord(Word.toLargeWord n))
53 :    
54 :     fun emitHiLo(hi,lo) = ( emitByte ((hi >> 0w8) & 0w255);
55 :     emitByte (hi & 0w255);
56 :     emitByte ((lo >> 0w8) & 0w255);
57 :     emitByte (lo & 0w255))
58 :    
59 :    
60 :     fun emitLong n = let
61 :     val w = itow n
62 :     in
63 :     emitHiLo((w >> 0w16), w & 0w65535)
64 :     end
65 :    
66 :     fun emitLongX n = let
67 :     val w = itow n
68 :     in
69 :     emitHiLo((w ~>> 0w16), w & 0w65535)
70 :     end
71 :    
72 :     fun emitString s = Word8Vector.app emitByte' (Byte.stringToBytes s)
73 :    
74 :     exception BadReal = IEEEReal.BadReal
75 :     val emitReal = emitString o IEEEReal.realconst
76 :    
77 :     fun emitAddr (INFO{addrOf,...}) (lab,k) = emitLongX (k + addrOf lab - !loc)
78 :    
79 :     fun define _ _ = ()
80 :    
81 :     fun mark() = emitLong(LargeWord.toInt(RS6000Spec.ObjDesc.makeDesc(
82 :     (!loc + 4) div 4,
83 :     RS6000Spec.ObjDesc.tag_backptr)))
84 :    
85 :     fun comment _ = ()
86 :    
87 :     fun emitInstr info = let
88 :     val don'tCare = 0
89 :     fun d_form(opcd,rt,ra,si) = let
90 :     val hi = (opcd << 0w10) || (itow rt << 0w5) || itow ra
91 :     val lo = si
92 :     in
93 :     emitHiLo(hi,lo)
94 :     end
95 :    
96 :     fun b_form(opcd,bo,bi,bd,aa,lk) = let
97 :     val hi = (opcd << 0w10) || (itow bo << 0w5) || itow bi
98 :     val lo = (itow bd << 0w2) || (itow aa << 0w1) || itow lk
99 :     in
100 :     emitHiLo(hi,lo)
101 :     end
102 :    
103 :     fun i_form(opcd,li,aa,lk) = let
104 :     val liLo = itow li & 0wx3fff
105 :     val liHi = (itow li ~>> 0w14) & 0wx3ff
106 :     val hi = (opcd << 0w10) || liHi
107 :     val lo = (liLo << 0w2) || (itow aa << 0w1) || itow lk
108 :     in
109 :     emitHiLo(hi,lo)
110 :     end
111 :    
112 :     fun x_form(opcd,rt,ra,rb,eo,rc) = let
113 :     val hi = (opcd << 0w10) || (itow rt << 0w5) || itow ra
114 :     val lo = (itow rb << 0w11) || (itow eo << 0w1) || itow rc
115 :     in
116 :     emitHiLo(hi,lo)
117 :     end
118 :    
119 :     fun xl_form(opcd,bt,ba,bb,eo,lk) = let
120 :     val hi = (opcd << 0w10) || (itow bt << 0w5) || itow ba
121 :     val lo = (itow bb << 0w11) || (itow eo << 0w1) || itow lk
122 :     in
123 :     emitHiLo(hi,lo)
124 :     end
125 :    
126 :     fun xo_form(opcd,rt,ra,rb,oe,eo',rc) = let
127 :     val hi = (opcd << 0w10) || (itow rt << 0w5) || itow ra
128 :     val lo = (itow rb << 0w11) || (itow oe << 0w10) ||
129 :     (itow eo' << 0w1) || itow rc
130 :     in
131 :     emitHiLo(hi,lo)
132 :     end
133 :    
134 :     fun a_form(opcd,frt,fra,frb,frc,xo,rc) = let
135 :     val hi = (opcd << 0w10) || (itow frt << 0w5) || itow fra
136 :     val lo = (itow frb << 0w11) || (itow frc << 0w6)
137 :     || (itow xo << 0w1) || itow rc
138 :     in
139 :     emitHiLo(hi,lo)
140 :     end
141 :    
142 :     fun m_form(opcd,rs,ra,rb,mb,me,rc) = let
143 :     val hi = (opcd << 0w10) || (itow rs << 0w5) || itow ra
144 :     val lo = (itow rb << 0w11) || (itow mb << 0w6) ||
145 :     (itow me << 0w1) || itow rc
146 :     in
147 :     emitHiLo(hi,lo)
148 :     end
149 :    
150 :    
151 :     fun cr_bits M.LT = 0
152 :     | cr_bits M.GT = 1
153 :     | cr_bits M.EQ = 2
154 :     | cr_bits M.SO = 3
155 :     | cr_bits _ = error "cr_bits"
156 :    
157 :     fun fcr_bits(M.FL,2) = 8
158 :     | fcr_bits(M.FG,2) = 9
159 :     | fcr_bits(M.FE,2) = 10
160 :     | fcr_bits(M.UN,2) = 11
161 :     | fcr_bits(M.FX,1) = 4
162 :     | fcr_bits(M.FEX,1) = 5
163 :     | fcr_bits(M.VX,1) = 6
164 :     | fcr_bits(M.OX,1) = 7
165 :     | fcr_bits _ = error "fcr_bits"
166 :    
167 :     fun immedLabOff labexp = let val labOff = M.labelValue info labexp
168 :     in
169 :     (labOff - !loc) div 4
170 :     end
171 :    
172 :     fun emitBranchcc (bool,Label16Off labexp,crbit) = let
173 :     val bo = if bool then 0x0c else 0x4
174 :     val lab = immedLabOff labexp
175 :     in
176 :     b_form(0w16,bo,crbit,lab,0,0)
177 :     end
178 :    
179 :     fun immed_eaValue(Immed16Op n) = itow n
180 :     | immed_eaValue(LabelOp lab) = itow(M.labelValue info lab)
181 :     | immed_eaValue(HiLabOp lab) = M.hiLabelValue info lab
182 :     | immed_eaValue(LoLabOp lab) = M.loLabelValue info lab
183 :     | immed_eaValue _ = error "immed_eaValue"
184 :     in
185 :     fn NOP => error "emitInstr: NOP"
186 :     | B lab24exp => let
187 :     val lab = M.labBranch24Off info lab24exp - (!loc div 4)
188 :     in
189 :     i_form(0w18,lab,0,0)
190 :     end
191 :     | BB(cc,bool,lab) => emitBranchcc(bool,lab,cr_bits cc)
192 :     | BBF(cc,cr,bool,lab) => emitBranchcc(bool,lab,fcr_bits(cc,cr))
193 :     | BR() => xl_form(0w19,0x14,don'tCare,don'tCare,16,0)
194 :     | LBZ(Reg rt,Reg ra,RegOp(Reg rb))=> x_form(0w31,rt,ra,rb,87,0)
195 :     | LBZ(Reg rt,Reg ra,ea) => d_form(0w34,rt,ra,immed_eaValue ea)
196 :     | L(Reg rt,Reg ra,RegOp(Reg rb)) => x_form(0w31,rt,ra,rb,23,0)
197 :     | L(Reg rt,Reg ra,ea) => d_form(0w32,rt,ra,immed_eaValue ea)
198 :     | LFD(Freg frt,Reg ra,ea) => d_form(0w50,frt,ra,immed_eaValue ea)
199 :     | LIU(_,RegOp _) => error "emitInstr: LIU"
200 :     | LIU(Reg rt,ui) => d_form(0w15,rt,0,immed_eaValue ui)
201 :     | MTSPR(LR,Reg rs) => x_form(0w31,rs,0x8,don'tCare,467,0)
202 :     | MTSPR(MQ,Reg rs) => x_form(0w31,rs,0,don'tCare,467,0)
203 :     | FMR(Freg frt,Freg frb) => x_form(0w63,frt,don'tCare,frb,72,0)
204 :     | MTFSB1 bt => x_form(0w63,bt,don'tCare,don'tCare,38,1)
205 :     | TRAP() => x_form(0w31,4,0,0,4,0)
206 :     | CAL(Reg rt,Reg ra,RegOp(Reg rb)) => xo_form(0w31,rt,ra,rb,0,266,0)
207 :     | CAL(Reg rt,Reg ra,ea) => d_form(0w14,rt,ra,immed_eaValue ea)
208 :     | STB(Reg rs,Reg ra,RegOp(Reg rb))=> x_form(0w31,rs,ra,rb,215,0)
209 :     | STB(Reg rs,Reg ra,ea) => d_form(0w38,rs,ra,immed_eaValue ea)
210 :     | ST(Reg rs,Reg ra,RegOp(Reg rb)) => x_form(0w31,rs,ra,rb,151,0)
211 :     | ST(Reg rs,Reg ra,ea) => d_form(0w36,rs,ra,immed_eaValue ea)
212 :     | STFD(Freg frs,Reg ra,ea) => d_form(0w54,frs,ra,immed_eaValue ea)
213 :    
214 :     | A(Reg rt,Reg ra,RegOp(Reg rb)) => xo_form(0w31,rt,ra,rb,0,10,0)
215 :     | A(Reg rt,Reg ra,ea) => d_form(0w12,rt,ra,immed_eaValue ea)
216 :     | AO(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,1,10,1)
217 :     | FAO(Freg frt,Freg fra,Freg frb) => a_form(0w63,frt,fra,frb,don'tCare,21,1)
218 :    
219 :     | SF(Reg rt,Reg ra,RegOp(Reg rb)) => xo_form(0w31,rt,ra,rb,0,8,0)
220 :     | SF(Reg rt,Reg ra,ea) => d_form(0w8,rt,ra,immed_eaValue ea)
221 :     | SFO(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,1,8,1)
222 :     | FSO(Freg frt,Freg fra,Freg frb) => a_form(0w63,frt,fra,frb,don'tCare,20,1)
223 :    
224 :     | MULSO(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,1,235,1)
225 :     | MULS(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,0,235,0)
226 :     | FMO(Freg frt,Freg fra,Freg frc) => a_form(0w63,frt,fra,don'tCare,frc,25,1)
227 :    
228 :     | DIVS(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,1,363,1)
229 :     | DIV(Reg rt,Reg ra,Reg rb) => xo_form(0w31,rt,ra,rb,0,331,0)
230 :     | FDO(Freg frt,Freg fra,Freg frb) => a_form(0w63,frt,fra,frb,don'tCare,18,1)
231 :    
232 :     | FNEG(Freg frt,Freg frb) => x_form(0w63,frt,don'tCare,frb,40,1)
233 :     | FABS(Freg frt,Freg frb) => x_form(0w63,frt,don'tCare,frb,264,1)
234 :    
235 :     | CMP(Reg ra,RegOp(Reg rb)) => x_form(0w31,0,ra,rb,0,0)
236 :     | CMP(Reg ra,ea) => d_form(0w11,0,ra,immed_eaValue ea)
237 :     | CMPL(Reg ra,Reg rb) => x_form(0w31,0,ra,rb,32,0)
238 :     | FCMP(Freg fra,Freg frb) => x_form(0w63,8,fra,frb,32,0)
239 :     | CROR(bt, ba, bb) =>
240 :     xl_form(0w19, fcr_bits(bt,2), fcr_bits(ba,2), fcr_bits(bb,2), 449, 0)
241 :    
242 :     | AND(Reg ra,Reg rs,RegOp(Reg rb)) => x_form(0w31,rs,ra,rb,28,0)
243 :     | AND(Reg ra,Reg rs, ea) => d_form(0w28,rs,ra,immed_eaValue ea)
244 :     | OR(Reg ra,Reg rs,RegOp(Reg rb)) => x_form(0w31,rs,ra,rb,444,0)
245 :     | OR(Reg ra,Reg rs,ea) => d_form(0w24,rs,ra,immed_eaValue ea)
246 :     | XOR(Reg ra,Reg rs,RegOp(Reg rb)) => x_form(0w31,rs,ra,rb,316,0)
247 :     | XOR(Reg ra,Reg rs,ea) => d_form(0w26,rs,ra,immed_eaValue ea)
248 :     | XORU(_,_,RegOp _) => error "emitInstr: XORU"
249 :     | XORU(Reg ra,Reg rs,ea) => d_form(0w27,rs,ra,immed_eaValue ea)
250 :    
251 :     | SL(Reg ra,Reg rs,RegShift(Reg rb)) => x_form(0w31,rs,ra,rb,24,0)
252 :     | SL(Reg ra,Reg rs,Int5Shift si) => m_form(0w21,rs,ra,si,0,31-si,0)
253 :     | SRA(Reg ra,Reg rs,RegShift(Reg rb)) => x_form(0w31,rs,ra,rb,792,0)
254 :     | SRA(Reg ra,Reg rs,Int5Shift si) => x_form(0w31,rs,ra,si,824,0)
255 :     | SRL(Reg ra,Reg rs,Int5Shift si) => x_form(0w31,rs,ra,si,696,0)
256 :     | SRL(Reg ra,Reg rs,RegShift(Reg rb)) => x_form(0w31,rs,ra,rb,665,0)
257 :     | _ => error "emitInstr"
258 :     end
259 :     end
260 :    
261 :    
262 :     (*
263 :     * $Log: rs6000mc.sml,v $
264 :     * Revision 1.4 1998/02/12 20:48:44 jhr
265 :     * Removed references to System.Tags.
266 :     *
267 :     * Revision 1.3 1997/11/14 21:48:10 jhr
268 :     * Restored the support for the Power architecture; the PowerPC code
269 :     * generator will be MLRisc based.
270 :     *
271 :     * Revision 1.2 1997/08/25 16:43:35 jhr
272 :     * Replaced some old Power architecture instructions with PowerPC instructions.
273 :     * This means that the Power architecture is no longer supported by this
274 :     * code generator. Also improved implementation of emitString.
275 :     *
276 :     * Revision 1.1.1.1 1997/01/14 01:38:45 george
277 :     * Version 109.24
278 :     *
279 :     *)

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